A NEW CMOS READOUT CIRCUIT FOR VO2-BASED UNCOOLED FOCAL PLANE ARRAYS

A new CMOS readout circuit for VO₂-based uncooled FPAs is presented in this paper. The on-chip readout circuit consists of three major parts: An input circuit of BCDI structure, a column-shared integration circuit of CTIA structure, and a common CDS output circuit. The simple configuration of the input circuit makes it possible to operate more circuits in parallel, and increases the integration time and number of pixels, the column-shared integration circuit which is suitable for small pixel size provides low noise, high gain, a highly stable detector bias, and high photon current injection efficiency, and the common CDS output circuit is utilized to reduce or eliminate low-frequency noise of the readout circuit. An experimental readout chip for 50-μm-pitch 32×32 element VO₂-based uncooled FPAs has been fabricated. The measurement results of the fabricated readout chip have successfully verified its readout function and excellent performance.     

Wafer-scale 3D integration of InGaAs photodiode arrays with Si readout circuits by oxide bonding and through-oxide vias

A new wafer-scale three dimensional (3D) integration technique, originally developed for Si, is applied to hybridize InP-based photodiode arrays with Si readout circuits. The infrared (IR) photodiodes consisted of an InGaAs absorption layer grown on the InP substrate and were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits to allow 3D integration in the Si fabrication facility. The finished 150-mm-diameter InP wafer was directly bonded to the SOI wafer and interconnected to the Si readout circuits by through-oxide vias (TOV). A 32 × 32 array with 6-μm pixel size was demonstrated. The 3D integration of InP with Si wafers achieved the smallest pixel size, which is less than a half of that can be achieved using conventional flip-chip bump bonding technique.     

An integrated readout circuit for personal dosimetry with phase-shift compensation technique to improve stability

In this paper an integrated CMOS readout circuit for a radiation detector in a personal dosimeter is presented. High counting rate and low power requirements make the stability of the conventional high-pass pulse shaper a big problem. A novel phase-shift compensation method is proposed to improve the phase margin. The principle of the compensation circuit and its influence on noise performance are analyzed theoretically. A readout chip with two channels of conventional structure and one channel of the proposed structure has been implemented in a 0.35 μm CMOS technology. It occupies an area of 2.113×0.81 mm². Measurement results show that the proposed channel can process up to 1 MHz counting rate and provide a conversion gain of about 170 mV/fC at a power dissipation of 330 μW with a 3.3 V power supply. Ac-coupled to a silicon PIN detector, it successfully detects β-rays.     

Micropower fully integrated CMOS readout interface for neural recording application

In this paper, we presented a micropower, small-size fully integrated CMOS readout interface for neural recording system. A crucial and important module of this system is the amplifier circuit with low-power low-noise. We describe a micropower low-noise readout circuit using an active feedback fully differential structure to reject the 1/f noise and large DC-offsets, the substrate-bias technology to further decrease the noise and power of the neural recording amplifier. Therefore, the neural amplifier with micropower low-noise and high input impedance is presented. The readout interface core, fully differential amplifier is implemented in 0.35-μm CMOS process, passes neural signals from 10 Hz to 9 kHz with an input-referred noise of 4.3 μV_rms. The power consumption of single amplifier is 5.6 μW while consuming 0.03 mm² of die area. The low cutoff frequencies of the circuit can adjusted from 10 Hz to 400 Hz, and the high cutoff frequencies form 4 kHz to 9 kHz.     

Design and testing of a self-powered 3D integrated SOI CMOS system

A self-powering 3D integrated circuit built using an SOI CMOS process is presented. The 3D integrated circuit has three tiers connected by vertical vias through the intertier oxides. The circuit elements are a photodiode array, a charge-integrating capacitor, and a local oscillator with an output buffer, each on a separate tier. The final system size is 250 μm × 250 μm × 696 μm. Our results demonstrate the circuit as a feasible proof-of-concept 3D “system”. The photodiode array stores charge on the capacitor and powers the oscillator as designed.     

Crosstalk Characterization in Geiger-Mode Avalanche Photodiode Arrays

Following our work on Geiger-mode avalanche photodiode arrays, we have recently been dealing with the crosstalk issue in newly developed dense arrays with a minimum distance between pixel centers of 84 mum. In this paper, we present our crosstalk measurement approach, including the experimental setup and the offline calculation methods. Different characterizations of the crosstalk probability P_CT versus capacitance have been performed to extrapolate the P_CT when no measurement setup loads the pixels. We also present results regarding the crosstalk probability versus pixel distance and bias. Moreover, by adopting a slightly different approach, the probability density decay time has been measured to investigate about crosstalk origin.     

A 640 by 480 Pixels Readout Circuit for IR Imaging

A readout circuit for a 640 × 480 pixels FPA (focal plane array) has been successfully designed, fabricated and tested. The circuit solution is based on a per pixel source-follower direct injection (SFDI) pre-amplifier. Signal multiplexing is performed in both X and Y direction. The pixel size is 25 m × 25m. The chip is optimized for a QWIP (quantum well infrared photodetector) operating at a temperature of 70 K. The circuit has been realized in a standard 0.8 m CMOS process.     

Design and evaluation of current-mode image sensors in CMOS-technology

Three different current-mode-output CMOS image sensor structures comprising of a pixel cell and an appropriate readout circuit have been analyzed and compared with regard to their noise behavior, fixed-pattern noise (FPN), and the dynamic range. First, a standard integrating pixel cell with a readout circuit containing a voltage-to-current converter is proposed. Second, a pixel cell based on a switched current cell is analyzed. The third sensor cell uses a feedback loop to control the reverse bias voltage of the photodiode to reduce the settling time of the pixel cell and the influence of the photodiodes's dark current. The necessary amplifier is partly located in the pixel cell and partly in the readout circuit. In all sensors, correlated double sampling is used to suppress the FPN.     

面向384×288面阵型红外读出电路的低功耗设计

介绍了一种面向384×288 CMOS面阵性红外读出电路的低功耗设计.针对探测器的特点(输出阻抗约100kΩ,积分电流约100nA),新提出并实现了一种四像素共用BDI的QSBDI(Quad-share BDI)像素结构.在QSBDI结构中,4个相邻的像素共用一个反馈放大器,从而实现了高注入效率、稳定的偏置、较好的FPN特性和低功耗.另外该384×288读出电路还支持积分然后读出、积分同时读出功能,还有两个可选择的增益以及4种窗口读出模式.128×128的测试读出电路已完成设计、加工和测试.电路使用CSMC0.5μm DPTM工艺流片,测试结果表明在每个子阵列输出的峰峰差异仅为10mV.在4MHz的工作频率下,像素级引入的功耗仅为1mW,芯片的整体功耗也只有37mW,实现了低功耗设计.     

A 7-bit 500 kS/s 1 V micro-power SAR A/D converter for pixel systems

The design and measurement results of a micro-power successive approximation charge redistribution ADC implemented in CMOS 180 nm technology are presented. The project has been optimized for very low area occupancy in order to utilize it in multichannel neural signal recording pixel systems for future application. The design has been fabricated, experimentally characterized and it exhibits good performance, especially from the silicon area occupation point of view. The presented converter achieves 500 kS/s sampling rate with ENOB of 6.54 at 4.45 μW and occupies only 90 μm×95 μm of silicon area.     

SPAD阵列读出电路关键技术与发展趋势(特邀)

首先针对SPAD阵列读出电路的特点,将电路主要分成接口电路与信号处理电路两大部分,其次根据单光子雪崩光电探测器的阵列的不同应用场景,阐述了集成读出电路中核心电路模块设计的关键技术。分别从SPAD的接口电路设计、两种典型应用成像模式(光子计时、光子计数)中核心电路的设计方面,详细分析此类电路的关键技术以及国内外研究团队在此类电路的研究进展与存在的问题。最后根据目前国内外研究的进展情况,分析了SPAD阵列集成读出电路的发展趋势以及各类电路存在的设计重点与难点,为SPAD阵列读出电路的设计提供一些参考。     

Visible blind p-π-n-n ultraviolet photodetectors based on 4H-SiC homoepilayers

p⁺-π-n⁻-n⁺ ultraviolet photodetectors based on 4H-SiC homoepilayers have been presented. The growth of the 4H-SiC homoepilayers was carried out in a LPCVD system. The size of the active area of the photodetectors was 300×300 μm². The dark and illuminated I-V characteristics had been measured at reverse biases form 0 to 20 V at room temperature, and the illuminated current was at least two orders of magnitude than that of dark current below 13 V bias. The peak value zones of the photoresponse were located at 280-310 nm at different reverse biases, and the peak value located at 300 nm was 100 times greater than the cut-off response value in 380 nm at a bias of 10 V, which showed the device had good visible blind performance. A small red-shift about 5 nm on the peak responsivity occurred when reverse bias increased from 5 to 15 V.     

A digital array based bit serial processor for arbitrary window size kernel convolution in vision sensors

The high speed and in-pixel processing of image data in smart vision sensors is an important solution for real time machine vision tasks. Diverse architectures have been presented for array based kernel convolution processing, many of which use analog processing elements to save space. In this paper a digital array based bit serial architecture is presented to perform certain image filtering tasks in the digital domain and hence gain higher accuracies than the analog methods. The presented method benefits from more diverse convolution options such as arbitrary size kernel windows, compared with the digital pulse based approaches. The proposed digital cell structure is compact enough to fit inside an image sensor pixel. When incorporated in a vision chip, resolutions of up to 12 bit accuracy can be obtained in kernel convolution functions with 35×28 μm² layout area usage per pixel in a 90 nm technology. Still, higher accuracies can be obtained with larger pixels. The power consumption of the approach is approximately 10 nW/pixel at a frame rate of 1 kfps.     

一个128×128CMOS快照模式焦平面读出电路设计

本文介绍了一个工作于快照模式的CMOS焦平面读出电路新结构——DCA(Direct-injection Charge Amplifier)结构.该结构像素电路仅用4个MOS管,采用特殊的版图设计并用PMOS管做复位管,既可保证像素内存储电容足够大,又可避免复位电压的阈值损失,从而提高了读出电路的电荷处理能力.由于像素电路非常简单,且该结构能有效消除列线寄生电容C_bus的影响,因此该结构非常适用于小像素、大规模的焦平面读出电路.采用DCA结构和1.2μm双硅双铝(DPDM-Double-Poly Double-Metal)标准CMOS工艺设计了一个128×128规模焦平面读出电路试验芯片,其像素尺寸为50×50μm²,电荷处理能力达11.2pC.本文详细介绍了该读出电路的体系结构、像素电路、探测器模型和工作时序,并给出了精确的HSPICE仿真结果和试验芯片测试结果.     

Short-Wave Infrared HgCdTe Avalanche Photodiodes

Short-wave infrared (SWIR) HgCdTe avalanche photodiodes (APDs) have been developed to address low-flux applications at low operating temperature and for laser detection at higher temperatures. Stable multiplication gains in excess of 200 have been observed in homojunction APDs with cutoff wavelengths down to 2.8???m and operating temperatures up to 300?K, associated with low excess noise F?<?1.3 and low 1/f noise. The measured dark current density at 200?K of 6.2???A/cm² is low enough to enable high-sensitivity single-element light detection and ranging (lidar) applications and time-of-flight imaging. Corresponding APD arrays have been hybridized on a readout integrated circuit (ROIC) designed for low-flux low-SNR imaging with low noise and frame rates higher than 1500?frames/s. Preliminary focal-plane array characterization has confirmed the nominal ROIC performance and showed pixel operability above 99.5% (pixels within ±50% of average gain). The bias dependence of the multiplication gain has been characterized as a function of temperature, cadmium composition, and junction geometry. A qualitative change in the bias dependence of the gain compared with mid-wave infrared (MWIR) HgCdTe has motivated the development of a modified local electric field model for the electron impaction ionization coefficient and multiplication gain. This model gives a close fit to the gain curves in both SWIR and MWIR APDs at temperatures between 80?K and 300?K, using two parameters that scale as a function of the energy gap and temperature. This property opens the path to quantitative predictive device simulations and to estimations of the junction geometry of APDs from the bias dependence of the gain.     

基于分时共享方案的640×512红外读出电路设计

大规模、高集成度的红外焦平面器件是实现高空间分辨率红外成像的核心。针对高集成度的红外焦平面技术发展,文中设计了一款15 m中心距640512的红外焦平面读出电路。为提升器件信噪比和积分时间,提出了一种22四个像元分时复用积分电容共享技术方案,单元采用直接注入（DI）结构作为输入级,使得读出电路最大电荷容量可达20 Me-/像元。电路有两档电荷容量可选,可满足不同光电流信号的读出要求。为了减小噪声的注入及提高缓冲器偏置电流的精度,为信号传输链路设计了相应的偏置电路。电路仿真结果表明,电路帧频108 Hz,功耗低于110 mW,线性度可高达99.99%。电路采用了CSMC 0.18 m 1P4M 3.3 V工艺加工流片,常温测试结果显示电路工作电流正常,偏置开关可控,功能正常。     

新型电流镜积分红外量子阱探测器读出电路的设计分析

设计了一种偏压可调电流镜积分(Current Mirroring Integration,CMI)红外量子阱探测器焦平面CMOS读出电路。该电路适应根据偏压调节响应波段的量子阱探测器,其中探测器偏压从0.61 V到1.55V范围内可调。由于CMI的电流反馈结构,使得输入阻抗接近0,注入效率达0.99;且积分电容可放在单元电路外,从而可以在一定的单元面积下,增大积分电容,提高了电荷处理能力和动态范围;为提高读出电路的性能,电路加入撇除(Skimming)方式的暗电流抑制电路。采用特许半导体(Chartered)0.35 m标准CMOS工艺对所设计的电路(16×1阵列)进行流片,测试结果表明:在电源电压为3.3V,积分电容为1.25pF时,电荷处理能力达到1.3×107个电子;输出摆幅达到1.76V;功耗为25mW;动态范围为75dB;测试结果显示CMI可应用于高性能FPA。     

First fully integrated 2-D array of single-photon detectors in standard CMOS technology

A two-dimensional (2-D) array (4 by 8) of single-photon avalanche diodes integrated in an industrial complementary metal-oxide-semiconductor (CMOS) process is presented. Each pixel combines a photodiode biased above its breakdown voltage in the so-called Geiger mode, a quenching resistor, and a simple comparator. The pitch between the pixels is 75 /spl mu/m and the diameter of each pixel is 6.4 /spl mu/m. The full integration allows reducing the number of charge carriers in a Geiger pulse. The electroluminescence responsible for optical crosstalks between pixels is then reduced leading to a negligible optical crosstalk probability. Thanks to the cleanness of the fabrication process, no afterpulsing effects are noticed. At room temperature, most of the pixels exhibit a dark-count rate of about 50 Hz. The detection probability is almost identical for all 32 pixels of the array with relative variation in the range of a few percents. This letter demonstrates the feasibility of an array of single-photon detectors sensitive in the visible part of the spectrum. Besides low production costs and compactness, an undeniable benefit lies in the potential to easily modify the design to fit a specific application. Furthermore, the CMOS integration opens the way to on-chip data processing.     

Noise suppression effect in an avalanche multiplication photodiode operating in a charge accumulation mode

A pixel configuration available to solid-state imagers using an avalanche multiplication photodiode operated in a charge accumulation mode, with each pixel as a photo-element, is proposed and stable avalanche multiplication gains over several tens are demonstrated by using a test circuit composed of discrete elements, equivalent to the pixel configuration. Moreover, it is found that the self-quenching effects inherent to the APD operating in this mode suppress the reset or avalanche induced excess noises, predominant in readout process and in charge accumulation process, respectively. These results are advantageous for a solid-state imager since the use of the avalanche multiplication simultaneously satisfies the two requirements of high sensitivity and wide dynamic range.<>     

Exposure parameters for MeV proton beam writing on SU-8

Proton beam writing was performed on a lithographic resist to determine the main parameters required to achieve the minimum feature size, maximum pattern lateral density and maximum aspect ratio. A 2.5 MeV proton beam focused to sizes between 1.5 and 2.5 μm was used to expose SU-8 negative resist. The number of protons per pixel was varied in the exposure of SU-8 with thicknesses between 5 and 95 μm. Patterns consisting of single pixels, single-pixel lines and multi-pixel areas with different densities were fabricated. The smallest structures achieved were posts 1.5 μm in diameter with 4:1 structure-space ratio in 15 μm thick resist and the highest aspect ratio structures of 20:1 in 40 μm resist were produced. It was found that the minimum feature size depended only on the beam size, and ±10% post size accuracy could be achieved within 40-70% variation of the number of protons. MeV proton beam allows a direct fabrication of complex shapes without a mask in single-step irradiation and, in addition, no proximity correction is needed. We present examples of MeV proton beam written single and multi-pixel microstructures with easily reproducible high aspect ratios and densities.