75 GHz 13.92 dBm InP DHBT 共射共基功率放大器

报道了基于InP基双屏质结双板晶体管(DHBT)工艺的四指共射共基75 GHz微波单片集成(MMIC)功率放大器,器件的最高振荡频率fmax为150 GHz.放大器的输出极发射极面积为15μm×4μm.功率放大器在75 GHz时功率增益为12.3 dB,饱和输出功率为13.92 dBm.放大器在72.5 GHz处输入为2 dBm时达到最大输出功率14.53 dBm.整个芯片传输连接采用共面波导结构,芯片面积为1.06 mm×0.75 mm.     

一种基于InP DHBT的CB Stack功率放大器设计北大核心

设计了一种中心频率为75 GHz的单级MMIC功率放大器，基于0.8μm InP DHBT器件制造，该器件ft/fmax为171/250 GHz。电路采用两层共基堆叠(CB Stack)结构，其中下层共基偏置采用基极直接接地，输入端发射极采用-0.96 V负压供电的方式，偏置电压Vc2为4 V。为了提高输出功率，上下两层器件进行了四指并联设计。此外，采用同样器件设计了另外一款下层共射的传统Stack结构电路。通过大信号仿真对CB Stack与国际上部分先进工艺下InP基的传统Stack结构电路性能进行对比，CB Stack结构在增益和峰值PAE上都比传统Stack有更好的表现。     

功率为16.9 dBm增益大于20 dB的InP DHBT W波段功率放大器

A two-stage MMIC power amplifier has been realized by use of a l-μm InP double heterojunction bipolar transistor(DHBT).The cascode structure,low-loss matching networks,and low-parasite cell units enhance the power gain.The optimum load impedance is determined from load-pull simulation.A coplanar waveguide transmission line is adopted for its ease of fabrication.The chip size is 1.5×1.7 mm~2 with the emitter area of 16×1μm×15μm in the output stage.Measurements show that small signal gain is more than 20 dB over 75.5-84.5 GHz and the saturated power is 16.9 dBm @ 79 GHz with gain of 15.2 dB.The high power gain makes it very suitable for medium power amplification.     

Analysis and design of high-power and efficient,millimeter-wave power amplifier systems using zero degree combiners

We present the analysis and design of high-power millimetre-wave power amplifier (PA) systems using zero-degree combiners (ZDCs). The methodology presented optimises the PA device sizing and the number of combined unit PAs based on device load pull simulations, driver power consumption analysis and loss analysis of the ZDC. Our analysis shows that an optimal number of N-way combined unit PAs leads to the highest power-added efficiency (PAE) for a given output power. To illustrate our design methodology, we designed a 1-W PA system at 45 GHz using a 45 nm silicon-on-insulator process and showed that an 8-way combined PA has the highest PAE that yields simulated output power of 30.6 dBm and 31% peak PAE.     

基于径向波导合成技术的W波段功率放大器设计

基于径向波导合成技术,设计了一款W波段功率放大器。功放采用4路氮化镓单片微波集成电路(MMIC)单片合成设计,在90 GHz处输出功率为3.7 W,合成效率为94.3%,具有较好的工程应用价值。     

Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique

This paper presents a design of a low power CMOS ultra-wideband (UWB) low noise amplifier (LNA) using a noise canceling technique with the TSMC 0.18 μm RF CMOS process. The proposed UWB LNA employs a current-reused structure to decrease the total power consumption instead of using a cascade stage. This structure spends the same DC current for operating two transistors simultaneously. The stagger-tuning technique, which was reported to achieve gain flatness in the required frequency, was adopted to have low and high resonance frequency points over the entire bandwidth from 3.1 to 10.6 GHz. The resonance points were set in 3 GHz and 10 GHz to provide enough gain flatness and return loss. In addition, the noise canceling technique was used to cancel the dominant noise source, which is generated by the first transistor. The simulation results show a flat gain (S₂₁>10 dB) with a good input impedance matching less than –10 dB and a minimum noise figure of 2.9 dB over the entire band. The proposed UWB LNA consumed 15.2 mW from a 1.8 V power supply.