The transient analysis of latch-up in CMOS transmission gate induced by laser

An analytical model of transient latch-up in CMOS transmission gate induced by laser is established. The time-dependent current characteristics of the parasitic silicon controlled rectifier (SCR) under different injected photocurrent are illustrated. The model analyzes the trigger conditions for latch-up and describes the dynamic process varying with time. The photocurrent threshold causing latch-up under different pulse widths and repetition frequencies is obtained, which agrees well with the experimental results reported in the literature.     

CMOS反相器在高功率微波下闩锁效应的温度影响

The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave （HPM） is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS in- verters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.     

Latch-up effects in CMOS inverters due to high power pulsed electromagnetic interference

Latch-up effects in two stage cascaded CMOS digital inverters due to high power pulsed electromagnetic interference, are reported. Latch-up was observed to occur at and above 25.5 dB m of pulsed interference at frequencies of 1.23 GHz and 4 GHz. When a latch-up event occurred, the devices failed to respond to the input logic signal even after the pulsed interference was removed. Devices required to be reset to return to normal operation. Latch-up for pulsed interference at the higher frequency of 4 GHz occurred at higher power levels, indicating a suppression of the interference effects at higher frequencies due to the by-pass path effects provided by the intrinsic device capacitances. High power interference induced excess carriers and the corresponding body currents that activated the parasitic bipolar transistor action were found to play a key role in triggering the latch-ups, and are proposed here as the main mechanism for the upsets. The parasitic resistances R1 and R2 for the cascaded inverters were calculated to be 4.3 and 2.8 kΩ, respectively, and the corresponding excess body currents triggering the latch-ups were 0.163 and 0.25 mA, respectively.     

Transient interferometric mapping of carrier plasma during external transient latch-up phenomena in latch-up test structures and I/O cells processed in CMOS technology

Substrate current distribution as trigger for external latch-up (LU) and transient latch-up (TLU) is analyzed by optical transient interferometric mapping (TIM) technique. The transient free carrier (plasma) concentration related to substrate current flow is studied for various guard-ring configurations and injection carrier type on special test structures and real I/O cells. TIM uncovers proximity effects in I/O cells causing substrate current crowding which are important for the definition of effective LU protection concepts.     

Transient characteristics of latch-up in bulk CMOS

Transient characteristics of the latch-up turn-on process in bulk CMOS are investigated. A measurement technique that evaluates the threshold trigger pulse current of latch-up and also observes latch-up turn-on transient waveforms is established. Through the comparison between experimental data and precise circuit simulation results, the main factors that determine transient latch-up characteristics are clarified as the base-emitter diffusion capacitors.     

Optically induced latch-up and other effects in CMOS UVEPROMs

Photographic flash-gun equipment used close to uncovered CMOS UVEPROMs can induce a variety of different failure modes including: (a) destructive latch-up, (b) transients in the output logic levels and in the supply current and (c) a nonde structive `output latching? effect. The mode of failure observed depends on the level of illumination used and on the logic state of the output pins.     

Temperature dependence of latch-up characteristics in LDD CMOS devices

The incremental rate of the latch-up holding current (Ih) with decreasing temperature is larger in the bulk substrate than in the epitaxial substrate. The substrate dependence is mainly due to the difference in the temperature coefficients of the material resistivity. Although Ihincreases significantly with decreasing temperature, the latch-up triggering voltage (Vtrig) in an inverter remains relatively constant, posing a limit for VLSI device miniaturization at low temperatures.     

Temperature dependence of latch-up phenomena in scaled CMOS structures

In this paper the temperature dependence of latch-up in a VLSI CMOS technology is studied. Both steady-state and pulse-induced dynamic trigger characteristics are presented showing a marked increase in latch-up resistance with decreasing temperature; in particular, a latch-up free condition is met for several structures at temperatures ranging between 100 and 200 K. The results of measurements of parasitic bipolar parameters and shunting resistances at different temperatures are reported, and their values are related to latch-up characteristics.     

Effect of internal chip stripes on susceptibility to supershort ultrawideband electromagnetic pulses

Reversible functional failure of an ATmega 8515 microcontroller (MC) is used to demonstrate the importance of internal stripes of chips in radio-transparent package in the analysis of susceptibility of microelectronic components to radio-frequency radiation. Experiments under different conditions for MC irradiation are performed and induced electric voltages are calculated using the simplest model of antenna reception. The calculated results are in qualitative agreement with the experimental data.     

Physical fundamentals of external transient latch-up and corrective actions

Detailed transient latch-up (TLU) analysis of external test structures show that a DC trigger does not necessarily reflect worst-case conditions. Furthermore, the classical guard ring latch-up protection approach fails for a transient trigger. In this contribution, the physical mechanism of TLU triggering is presented. The knowledge of physical phenomenons causing TLU triggering enables the derivation of design recommendations for integrated circuits.     

Analysis of latch-up neighborhood effects in VLSI CMOS input and output stages

The influence of electron and hole injection from neighboring structures on the latch-up hardness of an inverter in non-epitaxial CMOS is measured on specially designed test structures and compared with the results of two-dimensional numerical simulation provided by the program BAMBI. An analysis of the basic effects is given and remedial measures to avoid neighborhood effects are described.     

An analytic model of holding voltage for latch-up in epitaxial CMOS

For epitaxial CMOS in the latched state, the region between the anode and the cathode is conductivity modulated. In this case, the two-transistor model for the silicon-controlled rectifier (SCR) is not valid. However, a simplified analysis is possible because the well-substrate junction is obliterated by carriers. With this approach an analytic model is developed which can predict the holding voltage and its dependence on design parameters. The model is capable of predicting quantitatively the improvement in holding voltage with increased n+ -to-p+ spacing, thinner epi, substrate backbias, shallow trench, and silicided junctions and higher epi doping. The model explains a previously observed scaling law for the holding voltage.     

FDTD modeling of transient microwave signals in dispersive and lossy bi-isotropic media

In this paper, we present a novel finite-difference time-domain model of transient wave propagation in general dispersive bi-isotropic media with losses. The special properties of these materials may lead to new applications in microwave and millimeter-wave technology. While their frequency-domain properties have been well described in the literature, their time-domain behavior has only been modeled thus far for special sub-classes and monochromatic time dependence. We have validated our method by first computing time-harmonic wave propagation through a bi-isotropic medium and comparing it with analytical results. Agreement is typically better than 1%. We have then computed transient field propagation in a general lossy dispersive bi-isotropic medium.     

The impact of trench isolation on latch-up immunity in bulknonepitaxial CMOS

Numerical simulations have been used to show that two-dimensional effects can improve the latch-up immunity of deep trench-isolated, bulk, nonepitaxial CMOS. It is observed that the holding voltage is strongly influenced by trench dimensions and layout, which affect the two-dimensional spreading resistance of the conductivity-modulated well and substrate regions, which also changes the parasitic bipolar current gain. To increase the holding voltage, design parameters that are unique to deep trench isolation have been identified. The theoretical understanding that has been obtained can be exploited to design latch-up-free submicrometer CMOS at high packing densities without using expensive epitaxial substrates     

Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes

A technique for modeling the effect of variations in multiple process parameters on circuit delay performance is proposed. The variation in saturation current I_on at the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. The delay of a two-input NAND gate with 65 nm gate length transistors is extensively characterized by mixed-mode simulations, which is then used as a library element. Appropriate templates for the NAND gate library are incorporated in a general purpose circuit simulator SEQUEL. A 4-bit × 4-bit Wallace tree multiplier circuit, consisting of two-input NAND gates is used to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, by generating delay distributions, using an extensive Monte Carlo analysis. The use of linear interpolation and linear superposition is evaluated to study simultaneous variations in two and more process parameters. An analytical model for gate delays, in terms of device drive current I_on, is proposed, which can be used to extend this methodology for a generic technology library with a variety of library elements. The model is validated against Monte Carlo simulations and is shown to have a typical error of less than 0.1% for simultaneous variations in multiple process parameters. The proposed methodology can be used for statistical timing analysis and circuit simulation at the gate level.     

Application of transient interferometric mapping method for ESD and latch-up analysis

Transient Interferometric Mapping (TIM) tools are reviewed from a perspective of their particular application area and comparison to other transient optical analysis techniques. TIM studies on trigger behavior, current filamentation and failure modes in BCD DMOS and ESD protection devices under TLP and system-level-ESD – like pulses are overviewed. TIM analysis of CMOS ESD protection devices, in particular study of on-state spreading effect in 90 nm SCRs is also presented. Furthermore TIM investigations of substrate currents and parasitic SCR paths during transient latch-up events in 90 nm CMOS and BCD technology test structures and products are reviewed. Finally TIM studies of ESD and short-time self-heating phenomena in GaN HEMTs and lasers are also briefly mentioned.     

Prediction of delays induced by in-band RFI in CMOS inverters

Delays induced by radio frequency interference (RFI) in CMOS inverters are measured under radiated and capacitively coupled interference. Experimental and theoretical investigations of the effects of the RFI coupling mode (capacitive versus inductive) on the amount of induced delay are presented and a worst-case coupling mode is identified. A formula to predict delays caused by in-band low-level RFI in CMOS inverters is introduced. This formula uses experimentally determined parameters which are dependent on the coupling mode. The change in delay is computed as a function of the induced voltage disturbance, which in turn can be computed from the incident field using linear frequency-domain analysis. The formula accounts for the dependence of the induced delay on the phase and amplitude of the RFI signal as well as on the slew rate of the logic transitions. A delay growth phenomenon in a string of inverters is identified and characterized. A correction to the delay prediction formula is proposed in order to take this growth into account in worst-case predictions     

Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC

Measurements and mixed-mode simulations are used for the analysis of transient-induced latch-up (TLU) in CMOS IC. The transient interaction of the parasitic SCR with the surrounding off-chip and on-chip circuitry is investigated during positive and negative system-level ESD stress. It is shown, that sufficient on-chip decoupling and an active clamp can improve the TLU robustness of a circuit.     

Susceptibility of lithium-niobate modulator to high-power microwave pulses

The first measurement of the susceptibility of an off-the-shelf lithiumniobate intensity modulator to damage and disruption from high-power microwave pulses is reported. The device tested survived 1 kHz repetition rate pulses at 2.5 GHz centre frequency and 40 μs width up to 200 W peak power. The results are discussed in terms of material parameters and device characteristics.