First-principles study of GaAs(0 0 1)-β2(2 × 4) surface oxidation

Oxygen atom adsorption on GaAs(0 0 1)-β2(2 × 4) during initial surface oxidation is studied by density functional theory (DFT). The results show that one or two oxygen atom adsorption at back-bond sites satisfy the bond saturation conditions leading to no effect on the surface gap states. However, for an oxygen replacement of an As dimer atom at trough site or row site As dimer atoms, an As-As bond is broken. Mid gap states are produced leading to the Fermi level pining due to the unsaturated As dangling bonds.     

5–11 GHz CMOS PA with 158.9 ± 41 ps group delay and low power using current-reused technique

This paper proposes the design of a low group delay and low power ultra-wideband (UWB) power amplifier (PA) in 0.18 μm CMOS technology. The PA design employs two stages cascade with inductive peaking technique to provide broad bandwidth characteristic and higher gain while gain flatness can be achieved by connecting inter-stage circuit. A common gate current-reused technique is adopted at the first stage amplifier to achieve good input matching, low group delay and low power. The simulation results show that the proposed PA design has an average gain of 11.5 dB with flatness of ±0.4 dB from 5–11 GHz, while maintaining bandwidth of 4.2–12.3 GHz. An input return loss (S₁₁) less than −10.4 dB and output return loss (S₂₂) less than −9.5 dB, respectively are obtained. The PA design achieves excellent phase linearity (i.e., group delay variation) of ±41 ps and only consuming 17 mW power from 1.2 V supply voltage. A good output 1-dB compression point OP1 dB of 3.7 dBm is obtained. By using this method, the proposed design has low group delay variation and lowest power among the recently reported UWB CMOS PAs applications.     

Measurements of charge carrier mobilities and drift velocity saturation in bulk silicon of 〈1 1 1〉 and 〈1 0 0〉 crystal orientation at high electric fields

The mobility of electrons and holes in silicon depends on many parameters. Two of them are the electric field and the temperature. It has been observed previously that the mobility in the transition region between ohmic transport and saturation velocities is a function of the orientation of the crystal lattice.This paper presents a new set of parameters for the mobility as function of temperature and electric field for 〈1 1 1〉 and 〈1 0 0〉 crystal orientation. These parameters are derived from time of flight measurements of drifting charge carriers in planar p⁺nn⁺ diodes in the temperature range between −30 °C and 50 °C and electric fields of 2 × 10³ V/cm to 2 × 10⁴ V/cm.     

An ultra-wide-band 3.1-10.6 GHz LNA design in 0.18 μm SiGe BiCMOS

A two-stage monolithic ultra-wide-band (UWB) low-noise-amplifier (LNA) designed for MB-OFDM in 0.18 μm SiGe BiCMOS process is presented. With an optimized configuration combining advantages of RES-feedback and LC-ladder matching structure, the adjustable wide input matching is got and noise figure (NF) is controlled to a relevant low status. The measured S21 is from 7.6 to 14.2 dB over the 3-11 GHz operating band, NF is from 3.2 dB to 4.8 dB. With a 2.5 V power supply, the LNA has an overall power consumption of 14.5 mW.     

Outage probability analysis of multi-hop relayed wireless networks over η − μ fading channels

In this paper, we study the outage probability of multi-hop relayed wireless networks assuming independent but not necessarily identically distributed η − μ fading channels. In our analysis, we consider both regenerative and non-regenerative relays. To this end, we provide a novel expression for the moment generating function (MGF) of the reciprocal of the end-to-end signal-to-noise ratio (SNR) and we then use this expression to evaluate the end-to-end outage probability of the non-regenerative network via numerical inversion of the Laplace transform. Moreover, we provide a novel expression for the end-to-end outage probability of the regenerative network. It is worth mentioning here that the derived expressions can be reduced to several other expressions, such as Rayleigh, Nakagami-m, Hoyt, and One-sided Gaussian fading channels. Numerical and simulation results are provided to show the tightness of the derived expressions.     

Design of a 30 GHz rotary traveling wave oscillator with improved frequency tuning range in 0.18 μm CMOS technology

In this paper, the operation of rotary traveling wave oscillators is analyzed, the general oscillation condition is derived, and analytical formula for the oscillator loss is presented. Based on this analysis, switched transmission line is employed to extend the output frequency tuning range. Post-layout simulation shows a frequency tuning range of 3.1 GHz in the vicinity of 30 GHz. The proposed half-quadrature VCO exhibits a phase noise better than −102.2 dBc/Hz at 1 MHz offset frequency. The VCO provides an output power level ranging from −6 to −2.5 dBm with drawing 15.2 mA of dc current from a 1.8 V power supply.     

A dual front-end for the new GPS/GALILEO generation in a 0.35 μm SiGe process

A highly integrated, low-power GALILEO/GPS front-end for the new generation of positioning services has been designed using a 0.35 μm SiGe process. First an analysis of the current and future GPS and GALILEO signals is presented in order to show the interoperability between both systems and to set the requirements for the entire front-end. The receiver has been implemented using a 6 MHz bandwidth low IF architecture whose IF frequency is 4.092 MHz after digitalization. The ESD protected RF front-end exhibits a voltage gain of 103 dB and an SSB noise figure of 3.7 dB, which makes it suitable for high-sensitivity applications. The achieved power consumption is only 66 mW from a 3 V voltage supply and 38 mW if the internal dual-gain LNA is switched off with no compromise with performance and with a minimal amount of external components.     

A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme

This paper presents a low-power 10-bit 70-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a novel energy-efficient capacitor-switching scheme. Compared to the conventional scheme, the proposed split-capacitor V_cm-based capacitor-switching scheme can reduce the capacitor-switching energy by about 92% with better monotonicity. Meanwhile, full-custom SAR logic and registers, variable-delay self-timing cell and dynamic comparator with proposed two-segment DC offset correction scheme are also implemented to improve the conversion speed and accuracy requirements. The prototype was fabricated in 65-nm 1P9M CMOS technology. Measurement results show a peak signal-to-noise-and-distortion ratio (SNDR) of 53.2 dB, while consuming 960 μW from 1.2 V supply voltage. The figure of merit (FoM) is 36.8 fJ/conversion-step and the total active area is only 220×220 μm².     

Dilute nitrides and 1.3 μm GaInNAs quantum well lasers on GaAs

We present epitaxial growth of GaInNAs on GaAs by molecular beam epitaxy (MBE) using analog, digital and N irradiation methods. It is possible to realize GaInNAs quantum wells (QWs) with a maximum substitutional N concentration up to 6% and a strong light emission up to 1.71 μm at 300 K. High quality 1.3 μm GaInNAs multiple QW edge emitting laser diodes have been demonstrated. The threshold current density (for a cavity of 100×1000 μm²) is 300, 300, 400 and 940 A/cm² for single, double, triple and quadruple QW lasers, respectively. The maximum 3 dB bandwidth reaches 17 GHz and high-speed transmission at 10 Gb/s up to 110 °C under a constant voltage has been demonstrated.     

A 3–5 GHz low-power high-speed radiated power tuning UWB transmitter

To satisfy the different radiated power requirements for the ultra-wideband (UWB) data transmitting in the implantable electronic devices or the wireless component interconnections, a novel low-power high-speed UWB transmitter with radiated power tuning was proposed. The tunable radiated power is achieved by a UWB RF buffer with a peak value controller. The designed low-complex narrow pulse generator and digital ring on–off VCO ensure a high speed transmitting. The low power is realized by using a subtractor to eliminate the base-band component from the output of the VCO and making the UWB RF buffer and the VCO operating in standby mode. The design was fabricated by a standard 0.18 μm CMOS technology. The test results show that the design can achieve maximum data-rate of 250 Mbps, frequency bandwidth from 3 to 5 GHz, radiated power tuning from −40 dBm to −60 dBm, low-power of 8 pJ/bit, and small circuit area of 0.18 mm².     

0.8 μW 12-bit SAR ADC sensors interface for RFID applications

The design and first measuring results of an ultra-low power 12 bit successive-approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are optmised for low power consumption. The power consumption is 0.52 μW from a 1.2 V supply with a sample clock of 3.125 kHz and 0.85 μW at 6.25 kHz. This gives 136 pJ per conversion or 66 fJ per conversion step. As per authors’ knowledge, 66 fJ per conversion step is the best reported so far.The ADC was realised in the NXP CMOS 0.14 μm technology; the area was 0.35 mm². Only four metal layers were used in order to allow 3D integration of the sensors.     

A 0.18 μm CMOS ring VCO for clock and data recovery applications

In this paper, a 3.125 GHz four stage voltage controlled ring oscillator is presented. The oscillator has been designed in a 0.18 μm CMOS process with a 1.8 V supply. Behavioral simulations predict an 18% tuning range for the oscillator, with −91 dBc/Hz phase noise at 1 MHz offset. Its power consumption has been simulated to be as low as 15.3 mW and the variation of its DC level of oscillation is 20 mV, which corresponds to 1.3% of its mean value. While consuming less area than an LC VCO, the proposed oscillator design achieves a more stable and reliable operation point.     

A low-power differential injection-locked frequency divider with output power flatness in 0.5 μm E/D-mode GaAs PHEMT

This study implemented an injection-locked frequency divider (ILFD) on Ka-band millimeter-wave communication systems in 0.5 μm enhancement/depletion-mode (E/D-mode) GaAs PHEMT technology. The ILFD presents a low-power design based on the differential-injection circuit topology without using any injectors. Compared with the conventional single-injection ILFD circuits, the proposed ILFD exhibits output power flatness and wide locking range characteristics with a power consumption of 0.9 mW under a 0.4 V supply. The self-oscillation frequency was chosen to be 20 GHz for divided-by-2 operation. The measured locking range is approximately 11.5 GHz ranging from 32.5 GHz to 44 GHz when the injection power level is 5 dBm. The locking range exhibiting a 3 dB power roll-off characteristic at output is 10.5 GHz ranging from 33 GHz to 42.5 GHz.     

A 1.33 μW 10-bit 200KS/s SAR ADC with a tri-level based capacitor switching procedure

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) using an energy-efficient tri-level based capacitor switching procedure is presented. The proposed switching procedure achieves 97.66% less switching energy when compared to the conventional method. The number of unit capacitors is reduced by a factor of 4 over that of conventional architecture as well. To make the power consumption of the comparator scale down with respect to the comparison rate, the fully dynamic comparator is used. Moreover, the dynamic logic circuit is implemented to further reduce the power of digital circuits. The ADC is implemented in a 0.18 μm 1P6M CMOS technology. At 1.0-V power supply and 200KS/s, the ADC achieves an SNDR of 60.54 dB and consumes 1.33 μW, resulting in a figure-of-merit (FOM) of 7.7 fJ/conversion-step. The ADC core occupies an active area of only 230×400 µm².     

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm², including all pads. The measured input return loss is kept below −11 dB, and the output return loss is −8 dB, from 3.1 to 10.6 GHz.     

A dual mode UHF EPC Gen 2 RFID tag in 0.18 μm CMOS

A dual mode UHF RFID transponder in 0.18 μm CMOS conforming to the EPC Gen 2 standard is presented. Low voltage design of the analog and digital blocks enables the chip to operate with a 1 V regulated voltage and thus to reduce the power consumption. The novel dual mode architecture enables the chip to work in passive and battery-assisted modes controlled by the reader. A custom Gen 2 based command switches the operation mode of the circuit. By using a special clock calibration method the chip operates from 1.2 to 5 MHz clock frequency. Several low power techniques are employed to reduce the power consumption of the chip which is essential in passive RFID tags. Measurement results show that the chip consumes 12 μW at 1 V supply voltage when it communicates with the reader. The chip is fabricated in 0.18 μm standard CMOS technology and occupies 0.95 mm² die area.     

Total ionizing dose effect in 0.2 μm PDSOI NMOSFETs with shallow trench isolation

This paper presents the total ionizing dose radiation performance of 0.2 μm PDSOI NMOS devices under different bias conditions. The hump effect is observed in the transfer characteristic of the back gate device instead of the front gate device after radiation. A STI bottom corner parasitic transistor model is proposed to explain this phenomenon. It also provides a simple way to extract the effective sheet charge density along the STI sidewall. Three-dimensional simulation was applied to explain the radiation effect. It shows that charge trapped in the shallow trench isolation, particularly at the bottom region of the trench oxide where the STI and the BOX are connected, is the dominant contributor to the off-state drain-to-source leakage current. The dimension of the transistor plays an important role on influencing the device’s performance after radiation. Larger off-state leakage current and radiation induced threshold voltage shift are reported in the narrow channel device than in the wide channel one. Different TID responses due to the STI process variation are also discussed.     

A new 0.35 μm CMOS electronic interface for wide range floating capacitive and grounded/floating resistive sensor applications

In this paper we propose a novel interface circuit suitable for the read-out of both wide range floating capacitive and grounded/floating resistive sensors. This solution, employing only two Operational Amplifiers (OAs) as active blocks and some passive components, is based on a square-wave oscillating circuit topology which, instead of a voltage integration typically performed by other solutions in the literature, operates a voltage differentiation. Therefore, the proposed circuit, performing an impedance-to-period (Z–T) conversion, results to be suitable as first analog front-end for both wide variation capacitive (e.g., relative humidity) and resistive (e.g., gas) sensors. Its sensitivity and dynamic range can be easily set through external passive components. Preliminary experimental measurements, which have characterized and validated this solution, have been conducted through a suitable prototype PCB fabricated with discrete commercial components. Then, the proposed interface has been also designed at transistor level, in a standard CMOS technology (AMS 0.35 um), developing a single-chip integrated circuit with low-voltage (1.8 V, single supply) low-power (about 350 μW) characteristics in a very small silicon area (lower than 0.6 mm²) which results to be suitable for sensor array configurations and portable applications. Further experimental results, achieved utilizing commercial sample resistors and capacitors to emulate sensor behavior, have shown a linear trend and a satisfactory accuracy in the evaluation of floating capacitive (in the range 10 pF–1 μF), grounded resistive (in the range 150 kΩ–1.5 MΩ) and floating resistive (in the range 10 MΩ–1 GΩ) variations, also when compared to other solutions presented in the literature. The satisfactory interface behavior has been also confirmed by the measurement of both relative humidity through the commercial sensor Honeywell HCH-1000 (capacitive) and carbon monoxide CO through the commercial air quality sensor FIGARO TGS-2600 (resistive).     

An investigation into the crystallization and electric flame-off characteristics of 20 μm copper wires

Copper wires are used in electronic packaging, however the workability and reliability still need to be improved. This work investigates the microstructural characteristics and mechanical properties of annealed wires and un-annealed wires. In addition, the interface bonding characteristics of Al pads are also studied. Experimental results indicate that at the two annealing conditions of 610 °C/0.02 s and 510 °C/0.4 s, 20 μm copper wires possessed a fully annealed structure. Compared with the un-annealed wire, the annealed tensile strength and the annealed hardness decreased, and the annealed elongation increased. Through thermal crystallization, the matrix structure transformed from long, thin grains to equiaxed grains and a few annealed twins. The microstructure of the free air ball (FAB) after an EFO process consisted of column-like grains, and grew from the heat-affected zone (HAZ) to the Cu ball. As for bonding testing, the pull strength of the bonded samples increased with increasing the Al film thickness (from 76 nm to 800 nm).     

A DC offset and CMRR analysis in a CMOS 0.35 μm operational transconductance amplifier using Pelgrom's area/accuracy tradeoff

Nonideal factors which play a key role in performance and yield in high-precision operational amplifiers are rigorously investigated. Expressions for the offset voltage (V_os) and the common-mode rejection ratio (CMRR) are derived and correlated. The mismatch accuracy is analyzed for different transistor geometries in a CMOS OTA (operational transconductance amplifier) in 0.35 μm technology by using the Monte Carlo approach.