RFID芯片超声倒装封装技术研究

超声倒装是近年来芯片封装领域中快速发展的一种倒装技术,具有连接强度高、接触电阻低、可靠性高、低温下短时完成和成本低的优势,特别适合较少凸点的RFID芯片封装。在镀Ni/Au铜基板上进行了RFID芯片超声倒装焊接实验,金凸点与镀Ni/Au铜基板之间实现了冶金结合,获得了良好的力学与电气性能,满足射频要求。     

倒装芯片封装极具竞争力

随着倒装芯片封闭在成本和性能上的不断改进，加上键合金线价格的不断攀升，从手机到游戏机芯片的各种应用领域里，倒装芯片技术都变得更具竞争力。     

中国及亚太地区的倒装芯片封装技术

在亚太地区的中国和其它国家中,电子封装业和电子装配制造业方面增长的潜力仍然是巨大的。尽管西方国家和日本目前还控制着技术和市场发展的局势,然而通过发展合适的基础设施和制造能力,中国和亚太地区的其它国家将在新世纪内起到重要的作用,通过与各种传统的引线框架的比较,技术上我们对中国和其它亚太国家在开发倒装芯片封装所面的风险,要求及其优点进行了评估,阐述了开发倒装芯片封装技术的指导方针。     

步入主流领域的倒装芯片封装

倒装芯片与传统的引线键合封装技术相比较,可以拥有许多的优点,其中包括优异的导热性能和电性能、可以具有众多的IO接点、非常灵活地满足各种各样性能的基层、很好地利用现有的工艺技术、利用现有的基础装备,以及降低器件的外形尺寸。     

低成本的倒装芯片封装技术

倒装芯片互连技术有诸多优点，但是由于其成本高，不能够用于大批量生产中，所以使其应用受到限制。而本推荐使用的有机材料的方法能够解决上述的问题。晶圆植球工艺的诞生对于降低元件封装的成本起到了重要作用，此外，采用化学镀Ni的方法实现凸点底部的金属化也是可取的方法。本主要介绍了美国ChipPAC公司近几年来针对倒装芯片互技术的高成本而开发研制出的几种新技术。     

倒装芯片封装极具竞争力

随着倒装芯片封装在成本和性能上的不断改进,加上键合金线价格的不断攀升,从手机到游戏机芯片的各种应用领域里,倒装芯片技术都变得更具竞争力。     

倒装芯片及封装技术

介绍了倒装芯片的发展过程，其中主要对制造技术、封装方法及倒装焊焊点的可靠性进行了评述。     

倒装芯片集成电力电子模块的热设计

将倒装芯片(Flip Chip, FC)技术引入三维集成电力电子模块(Integrated Power Electronic Module,IPEM)的封装,可构建FC-IPEM.在实验室完成了由两只球栅阵列芯片尺寸封装MOSFET和驱动、保护等电路构成的半桥FC-IPEM.针对半桥FC-IPEM,建立半桥FC-IPEM的一维热阻模型,分析模块主要的热阻来源.运用FLOTHERM软件进行三维仿真,得到模块温度分布结果,给出优化模块热性能的依据.     

Increasing the bonding strength of chips on flex substrates using thermosonic flip-chip bonding process with nonconductive paste

Thermosonic flip-chip bonding process with a nonconductive paste (NCP) was employed to improve the processability and bonding strength of the flip-chip onto flex substrates (FCOF). A non-conductive paste was deposited on the surface of the copper electrodes over the flex substrate, and a chip with eight gold bumps bonded onto the copper electrodes by the thermosonic flip-chip bonding process.For the chips and flex substrates assembly, ultrasonic power is important in the removal of some of the non-conductive paste on the surface of copper electrodes during thermosonic bonding. Accordingly, gold stud bumps in this study were directly bonded onto copper electrodes to form successful electrical paths between chips and the flex substrate. A particular ultrasonic power resulted in some metallurgical bonding between the gold bumps and the copper electrodes, increasing the bonding strength. The ultrasonic power was not only to remove the NCP from the copper electrodes, but also formed metallurgical bonds during the thermosonic flip-chip bonding process with NCP.In this study, the parameters of the bonding of chips onto flex substrates using thermosonic flip-chip bonding process with NCP were a bonding force of 4.9 N, a curing time of 40 s, a curing temperature of 140 °C and an ultrasonic power of 14.46 W. The processability and bonding strength of flip-chips on flex substrates using thermosonic bonding process with NCP was verified in this study. This process has great potential to be applied to the packaging of consumed electronic products.     

热超声倒装焊在制作大功率GaN基LED中的应用

设计了适合于倒装的大功率GaN基LED芯片结构,在倒装基板硅片上制作了金凸点,采用热超声倒装焊接(FCB)技术将芯片倒装在基板上.测试结果表明获得的大面积金凸点连接的剪切力最高达53.93 g/bump,焊接后的GaN基绿光LED在350 mA工作电流下正向电压为3.0 V.将热超声倒装焊接技术用于制作大功率GaN基LED器件,能起到良好的机械互连和电气互连.     

温度因素对热超声键合强度的影响实验研究

主要研究了热超声键合过程中环境温度对键合强度的影响规律.分析了键合强度与键合温度之间的关系.实验研究发现,最佳键合"窗口"出现在200～240℃,此时键合强度可达20g左右.对推荐使用的大于5.4g的键合强度标准,本实验条件下可键合"窗口"为120～360℃.这些实验现象和分析结果为后期的键合参数匹配规律和系统动态特性研究打下基础.     

Reliability of assembly of chips and flex substrates using thermosonic flip-chip bonding process with a non-conductive paste

This study investigates the reliability of the assembly of chips and flex substrates using the thermosonic flip-chip bonding process with non-conductive paste (NCP). The high-temperature storage (HTS) test, the temperature cycling test (TCT), the pressure cooker test (PCT) and the high-temperature/high-humidity (HT/HH) test were conducted to examine the reliability of chips that are bonded on flex substrates. The environmental parameters used in the various reliability tests were consistent with the JEDEC standards. After the reliability tests, a peeling test was performed and the microstructure of the tested specimen observed to evaluate further the reliability.The bonding strength increased with the storage period in the HTS test. After the peeling test, a layer of copper electrodes was observed to be stuck on gold bumps over the fractured morphology of the chips when the chips and flex substrates were assembled using an ultrasonic power of 14.46 W, indicating that the bonding strength between the gold bumps and the copper electrodes was even higher than the adhesive strength of the layers that were deposited on the flex substrates. The HTS test yielded sufficient thermal energy to promote atomic interdiffusion between gold bumps and copper electrodes. Metallurgical bonding between the gold bump and the copper electrode occurred, improving the bonding strength. In the assembly of chips and flex substrates without the application of ultrasonic power in bonding process, the adhesive strength of NCP was highly reliable after HTS test, because the bonding strength was maintained after HTS test for various storage periods. The typical failure mode of PCT was interfacial delamination between NCP and flex substrates. Approximately 80% of the specimens exhibited full separation after PCT at 336 h when chips and flex substrates were assembled without applied ultrasonic power to the bonding process, revealing that the NCP cannot withstand the PCT and lost its adhesive strength. Applying an adequate ultrasonic power of 14.46 W in the bonding process not only improved the bonding strength, but also enabled the bonding strength to be maintained at high level after PCT. The high bonding strength was attributable to the strong bonding of the gold bumps on the copper electrodes after PCT for various storage periods. This experimental result demonstrates that ultrasonic power can increase the reliability of PCT on chips and flex substrates that were assembled with the NCP. The bonding strength of the gold bumps on the flex substrates did not change significantly after the TCT, revealing the great reliability of TCT on chips and flex substrates that were assembled using the thermosonic flip-chip bonding process with the NCP. The bonding strength of chips bonded to flex substrates increased with the storage periods of the HT/HH test if ultrasonic power was applied to bonding process. Neither delamination nor any defect at the bonding interface was observed. The reliability of the HT/HH test for chips bonded on flex substrates using the thermosonic flip-chip process with the NCP fulfills the requirements stated in the JEDEC standards.According to the experimental findings of various reliability tests, the chips that were bonded to flex substrates using the thermosonic bonding process with NCP met the JEDEC specifications; with the exception of the adhesive strength of NCP under PCT which must be improved.     

A Preliminary Electron Backscatter Diffraction Study of Microstructures and Microtextures Evolution during Au Stud and Flip Chip Thermosonic Bonding

Microstructures and microtextures of the gold wire, free air ball, Au stud bumps and flip chip bonding bumps were analyzed using Electron Backscatter Diffraction (EBSD). It is demonstrated that process parameters, such as bonding power, force and temperature have significant influences on the microstructure and microtexture of gold bumps. The non-uniform deformation, the associated microstructure defects and the local textures of the Au bumps under the vertical force and the horizontal ultrasonic wave applied are presented and discussed.     

Mechanism of Wafer Bonding Process

The basic force and bonding energy in wafer bonding have been revealed in this study.The basic cause for bonding contributes to the interatomic attractive forces between surfaces or the rduction of surface energies.The amplitude of roughness component can not exceed the criterion if wafer pair is bondable.The bonding behavior and challenge during annealing have been investigated.     

采用热压焊工艺实现金凸点芯片的倒装焊接

金凸点芯片的倒装焊接是一种先进的封装技术.叙述了钉头金凸点硅芯片在高密度薄膜陶瓷基板上的热压倒装焊接工艺方法,通过设定焊接参数达到所期望的最大剪切力,分析研究互连焊点的电性能和焊接缺陷,实现了热压倒装焊工艺的优化.同时,还简要介绍了芯片钉头金凸点的制作工艺.     

统计过程控制技术在键合工序中的应用

键合工序是半导体器件生产中的关键工序,采用统计过程控制(SPC)技术对关键工序进行监控是保持生产线稳定、减少质量波动的有力工具,可以提高产品的成品率和可靠性。在现有工序状态下采集键合拉力数据,计算和分析键合工序的工序能力指数,进行工艺调整和改进,直到工序能力指数Cpk≥1.33。选择计量控制图,对键合拉力数值进行监控,发现工序失控时,分析原因并及时采取纠正预防措施,保证工艺的一致性和稳定性,提高工艺成品率。     

引线键合工艺参数对封装质量的影响因素分析

分析讨论了封装过程中质量的影响因素与机理,参数间的相互耦合、干扰问题,指出了其对合理设定工艺参数、提高质量和合格率的重要作用.对目前国内外引线键合研究进行较为深入地分析,为进一步研究封装过程多因素影响规律、动态建模和实时监控奠定了基础.     

铜线压焊工艺防氧化问题研究

分析了集成电路封装压焊工艺中引起铜线氧化而造成工艺不稳定的各种原因并提出了解决方法。从设备、制具、材料、工艺等方面,采用分析铜球形状的方法,研究了不同气体保护装置、气体流量、烧球参数等对铜线成球及氧化的影响;确定了防止铜线氧化的最有效措施及其他改善方法,并通过实验对比及生产跟踪证实了所述措施与方法的有效性。