Σ-Δ A/D转换器在软件无线电移动终端中的应用

A/D转换器是基于软件无线电的多模移动终端中的关键器件.文章简要描述了移动通信信号特征,对闪烁型A/D转换器(Flash ADC)和Σ-Δ A/D转换器的性能进行了详细分析与比较,指出Σ-Δ A/D转换器可以更好地满足多模移动终端中对大动态范围A/D转换的要求.     

TM7 A／D适配器的工作原理及调试A／D测试程序的探讨

1 引言随着数字技术的不断发展和计算机在信号处理、控制等领域中的广泛应用,越来越多的过去由模拟电路所实现的工作,今天将由数字电路或计算机来处理。所以将模拟信号转换为数字量的A/D转换器的需求量大大增加。而对A/D转换器测试的要求也比以前更加迫切。我     

高速D/A转换器动态参数测试方法研究

对基于逻辑分析仪和频谱分析仪的高速D/A转换器的动态参数测试方法进行了理论分析和测试实践。通过编程,由逻辑分析仪给D/A转换器提供单一频率的数字正弦波和时钟信号;通过频谱分析仪,对D/A转换器输出模拟信号采样,进行快速傅里叶变换,分析得到D/A转换器的动态参数特性。实验证明,该方法能快速测试高速D/A转换器的动态参数,在实际应用中可获得良好的效果。     

用AD9054实现高速A/D转换

高速A/D转换是雷达实时成像系统的重要组成部分,其功能是通过高速A/D转换器完成对雷达回波信号的实时量化,将雷达接收机输出的回波模拟信号转换成数字信号。本文主要讨论采用AD公司的AD9054实现成像处理器的A/D转换。目前,电路板已经调试完毕,性能指标达到了要求。     

全自动声速测定中的信号采集

本文针对传统声速测量的不足之处,对测量仪器进行改进,实现其自动化测量。对超声换能器接收端接收的信号进行信号分析,推断出A/D采样频率大小对采样效果的影响,选择合适的放大器对信号进行处理,使之符合A/D转换器的参数要求。通过硬件电路设计,将信号放大、A/D转换,读出A/D转换的数据,拟合出超声波信号,并将数据输入计算机,通过一定的算法计算出声速。     

用AD9054实现高速A/D转换

高速A/D转换是雷达实时成像系统的重要组成部分,其功能是通过高速A/D转换器完成对雷达回波信号的实时量化,将雷达接收机输出的回波模拟信号转换成数字信号.本文主要讨论采用AD公司的AD9054实现成像处理器的A/D转换.目前,电路板已经调试完毕,性能指标达到了要求.     

基于FPGA的实时数字化光纤传输系统

提出一种实时数字化光纤传输系统,该系统分为发送端和接收端。发送端用A/D转换器将输入的模拟信号数字化,再用FPGA对数据进行处理,并通过光纤传输。同时,FPGA还控制A/D转换器的工作。接收端用串行收发器TLK1501对接收数据进行解码处理,还原有效信号。实验表明,该系统实时性好、信号传输误码率低、工作性能稳定、抗干扰性强,系统具有可行性和有效性。     

基于单片机和555定时器的A/D转换器设计

为克服在A/D转换中输入电压范围窄的问题,介绍了一种采用单片机AT89C51和NE555定时器构成的A/D转换器.详细分析了其工作原理和A/D转换的特性.该A/D转换器对低频输入信号在较高电压范围内具有一定的实用价值.     

基于模拟余差的7位200MS/s分级折叠式A/D转换器

提出一种基于模拟余差的分级折叠式A/D转换器,对其原理和电路结构进行了分析,阐述了提高A/D转换器性能的关键问题.测试结果表明,设计的A/D转换器转换速率为200 MS/s;在输入信号为6.0 MHz时,信噪谐波比(SINAD)为45.1 dB,有效位数(ENOB)为7.2位.给出了A/D转换器电路的具体结构,以及测试波形和动态性能参数测试结果.     

嵌入式微控制器片内A/D转换器的应用研究

介绍了微控制器片内A/D转换器的结构特点,深入分析了模拟输入信号源内阻对采样过程的影响、模拟输入信号源的大小与极性是否符合A/D转换器对输入信号的要求以及工作电源变化对转换精度的影响等方面问题,并提出解决方法.     

Analog to digital converter for high density neural signal recording front-end in 90 nm

High-fidelity recording of neural signals requires varying levels of signal gain to capture low-amplitude single-unit activity in the presence of high-amplitude population activity. A floating-point approach has been used to widen the dynamic range of analog-to-digital converters (ADC) designed for this application. In this paper we present an ADC, designed for multi-channel, portable neural signal recording systems. To achieve low power consumption, small die area and wide dynamic range, an ADC based on a time-based algorithm, combined with a floating-point pipelined structure has been designed and simulated. A conventional variable-gain amplifier (VGA) stage has been eliminated in favor of a reference-current in a time-based ADC architecture. The 12-b pipelined time-based floating-point ADC has been designed with a 7-b mantissa and an exponent that provides an additional 5 bits of dynamic range. The mantissa is determined by a uniform 7-b pipelined time-based analog to digital converter. The ADC chip was designed and simulated in a 90 nm CMOS process, which occupies an active area of 360 μm × 550 μm, and consumes 7.8 μW at 1.2 V in full-scale conversion.     

Current mode ADC design in a 0.5-μm CMOS process

This paper presents a pipelined current mode analog to digital converter (ADC) designed in a 0.5-μm CMOS process. Adopting the global and local bias scheme, the number of interconnect signal lines is reduced numerously, and the ADC exhibits the advantages of scalability and portability. Without using linear capacitance,this ADC can be implemented in a standard digital CMOS process; thus, it is suitable for applications in the system on one chip (SoC) design as an analogue IP. Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256μA. Adopting the histogram testing method, the ADC was tested in a 3.3 V supply voltage/±64μA quantization range and a 5 V supply voltage/±256μA quantization range, respectively. The results reveal that this ADC achieves a spurious free dynamic range of 61.46dB, DNL/INL are -0.005 to +0.027 LSB/-0.1 to +0.2 LSB, respectively, under a 5 V supply voltage with a digital error correction technique.     

A 20 b dynamic-range floating-point data acquisition system

The design and engineering of a floating-point data-acquisition system are described. The system has both automatic gain and software-programmable gain adjustment features. In automatic gain adjustment mode, the gain is set automatically dependent on the input amplitude so that the full conversion resolution is maintained irrespective of the signal dynamic range. A high-speed flash ADC with an approximately 35 ns conversion time is used to convert the signal quickly into 8 b data. A programmable array logic (PAL) then transfers this 8 b digital data into 12 b information for setting the gain of the variable-gain amplifier. The amplifier gain settings are all powers of two; thus, the normalization of the digitized data requires only a bit shifting operation and no complex software division. The gain information and the 12 b sampling ADC output increase the dynamic range to 20 b. The software package includes commands needed for the system initiation, automatic gain or software programmable gain selection, sampling and conversion, and data normalization     

机场天气雷达双通道数字中频处理系统的实现

机场天气雷达要求能够从复杂的天气环境中识别不同的天气状况以保障航空飞行安全,其接收机大动态以及抗噪性能设计对雷达至关重要。在分析模数转换器（ADC）对雷达中频接收机动态范围制约的基础上,根据中频带通采样和数字下变频的原理,实现了基于现场可编程门阵列的双通道ADC采样数字中频处理系统,并给出了系统的设计原理、方法以及测试结果。通过对双通道ADC采样的数字中频处理系统的实现,能够很好地提高天气雷达接收机的动态范围,并应用于机场多普勒天气雷达数字中频接收机。     

基于流水线ADC的高速数据采集系统设计

由于流水线模数转换器（ADC）能在较低的功耗条件下实现中、高精度高速数据采样功能,因而被广泛应用于雷达、通信、医学成像、精确控制等技术领域的数据采集系统。文章介绍了流水线ADC的基本原理及其最新研究成果,并且基于流水线ADC完成了一种14位精度125Msps高速数据采集系统的设计。测试结果表明,该系统在75Msps采样...     

低功耗-高速-高精度SAR ADC的FoM函数研究

SAR ADC适合工作在中级转换速度(Msample/s,Gsample/s),是低功耗和高精度的信号处理应用的最佳选择.为了更好地指导折中设计,基于梳理传统SAR ADC的FoM(Figure of Merits)函数的优缺点,保持寻求最小优值的方式,突出压缩优值变化范围的新优点,利用4参数构造出新的SAR ADC的...     

A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver

This work presents a configurable time-interleaved pipeline architecture as an efficient solution for the ADC design in high data rate multi-standard radios. The ADC is implemented in a 0.25-/spl mu/m BiCMOS process as part of an integrated dual mode 802.11b/Bluetooth direct conversion receiver. Its structure can be configured to accommodate the different sampling rate and dynamic range requirements of both standards. The different techniques employed at the system and circuit levels to optimize the power consumption are described. An on-line digital calibration scheme is also incorporated to assure the conversion linearity and reduce mismatch among the parallel branches. The proposed ADC is a switched-capacitor implementation occupying an area of 2.1 mm/sup 2/. It achieves 60 dB/64 dB dynamic range at 44 MHz/11 MHz sampling frequency with a power consumption of 20.2 mW/14.8 mW for the 802.11b/Bluetooth baseband signals.     

A third-order Δ-Σ modulator using second-ordernoise-shaping dynamic element matching

A multibit Δ-Σ modulator is an attractive way of realizing a high-accuracy, high-speed, and low-power data converter. However, the overall resolution of the modulator is determined by the internal digital-to-analog conversion (DAC) linearity. Methods for high-order noise shaping, noise-shaping dynamic element matching (NSDEM), have been proposed in order to overcome this drawback. However, a real implementation has not been realized until now. This paper presents the actual circuit configuration of a tree-structured NSDEM (TNSDEM) technique, which is applied to a multibit Δ-Σ DAC and analog-to-digital converter (ADC) using a nine-level internal DAC. This is the first report of a Δ-Σ ADC and DAC using the second-order NSDEM method. The test chip of the third-order Δ-Σ ADC realizes a signal bandwidth of 100 kHz and a dynamic range of 79 dB in the ADC and 80 dB in the DAC. The test chip only consumes 9.6 mW in the ADC and 5.2 mW in the DAC with a 2.7 V power supply     

A digital pixel sensor array with programmable dynamic range

This paper presents a digital pixel sensor (DPS) array employing a time domain analogue-to-digital conversion (ADC) technique featuring adaptive dynamic range and programmable pixel response. The digital pixel comprises a photodiode, a voltage comparator, and an 8-bit static memory. The conversion characteristics of the ADC are determined by an array-based digital control circuit, which linearizes the pixel response, and sets the conversion range. The ADC response is adapted to different lighting conditions by setting a single clock frequency. Dynamic range compression was also experimentally demonstrated. This clearly shows the potential of the proposed technique in overcoming the limited dynamic range typically imposed by the number of bits in a DPS. A 64 /spl times/ 64 pixel array prototype was manufactured in a 0.35-/spl mu/m, five-metal, single poly, CMOS process. Measurement results indicate a 100 dB dynamic range, a 41-s mean dark time and an average current of 1.6 /spl mu/A per DPS.