一种适用于心电信号检测的斩波前置放大器

提出一种适合心电信号检测的低压、低功耗、低噪声、高共模抑制比的差分差值斩波前置放大器,包括偏置电路、主放大电路和时钟产生电路,其中,时钟产生电路包括张弛振荡器和两相非交叠时钟产生电路。该放大器采用斩波技术减小了低频1/f噪声,采用差分差值输入、交叉耦合结构增加了共模抑制比,采用T型电容反馈减小了芯片面积,优化了放大器性能。芯片采用SMIC 0.18 μm 1P6M CMOS工艺设计,使用PSS,PAC,PNOISE进行仿真分析。结果表明,放大器在1.8 V电源电压下,静态电流为35 μA,闭环增益为40.6 dB,共模抑制比为115 dB,输入等效噪声仅为950 nV(rms)(0.01~100 Hz),适用于心电信号检测领域。     

基于多重斩波电路的通信电源控制方法

改善通信电源输入电流的谐波和功率因数不仅可以减少对供电系统的污染、提高电源总体效率,同时有利于提高输出电压质量。采用功率因数校正技术可以有效抑制输入电流谐波、提高功率因数,但要求开关管具有较高的开关频率,因此只能应用在一些小功率场合。采用移相调制的多重斩波电路,可以提高等效开关频率,因此可应用在中大功率场合。文章介绍了一种具有功率因数校正的多重斩波电路的控制方法,该方法通过载波移相方式来提高等效开关频率,给出了仿真验证结果。     

一种低功耗低噪声仪表放大器的设计

基于SMIC 0.18 μm CMOS工艺,设计了一种用于电生理信号监测的低功耗、低噪声仪表放大器。采用两级放大结构和斩波技术,减小了低频闪烁噪声。引入波纹抑制负反馈环路,减小了斩波带来的波纹噪声。采用积分负反馈直流失调抑制(DCOC)环路,减小了电路的失调。采用自举技术,增大了电路的输入阻抗。该电路的功耗仅为600 nW,带内(0.5～500 Hz)噪声小于200 nV/Hz,CMRR大于105 dB,输入阻抗大于500 MΩ。     

准确度达0.02%的具125VCM和120dB CMRR仪表放大器

当需要进行高准确度差分输入测量时,可采用图1所示的电路.它特别适合于有可能出现高共模电压的换能器信号调理.该电路不仅具有斩波稳定型放大器A1的低失调和漂移,还采用了一个新颖的光耦合、开关电容器输入级,旨在实现传统设计无法达到的规格指标.在±125V的输入范围内,DC共模抑制超过了120dB,而且,增益准确度和稳定性由A1来设定.     

基于斩波调制的带隙基准电压源的设计

为提高白光LED驱动的输出精度,采用了一种基于斩波调制技术的带隙基准源.使用斩波技术,减小了带隙基准源中运放的失调电压所引起的误差,提高了基准源的精度.设计了有启动电路的偏置以确保基准电路能正常工作.该电路利用上海贝岭的0.6 μm标准CMOS工艺实现,使用Cadence公司的Spectre工具对电路进行仿真.结果表明,该带隙基准输入电压可达2～9 V,输入电压3.5 V时温度系数为9.5×10-6/℃.当斩波频率为500 kHz时,此带隙基准源的输出精度比普通放大器提高了66倍,可以在高精度白光LED驱动电路中使用.     

一种适合集成传感器的微弱信号读出放大器

设计了一种适用于低频集成传感器微弱信号检测的低噪声放大器。该电路应用斩波技术抑制低频噪声和失调，利用带通滤波器减少残余失调电压。电路采用0．8μm N阱CMOS工艺设计，并进行了实际流片。对试制样片进行了测试，测得电路的增益为37dB，等效输入噪声为56．4nV/√Hz。     

D类功放中输入斩波运放电路的设计

基于n阱0.5μm DPDM CMOS工艺,完成了D类音频功放中输入斩波运算放大器的设计.分析了D类系统对输入运放的设计要求,在此基础上确定了电路采用两级全差分结构实现.并加入斩波结构降低噪声.采用PTAT电流源提供运放的偏置电流,补偿运放跨导gm的温度漂移.在Cadence下的电路仿真表明,前级运放具有16 μV·Hz-1/2的等效输入噪声,开环增益达到117.3 dB.运放所在芯片经过PWM方式流片验证,测试结果显示,芯片THD达到0.58%(f=1 kHz、P.=1 W、VDD=5 V),电源抑制比为65 dB.     

一种斩波稳定4阶单环Σ-Δ调制器

设计了一种适用于加速度计接口电路的全差分Σ-Δ调制器。该电路基于1位量化的4阶单环前馈结构,利用根轨迹法分析了该高阶系统的稳定性,采用斩波稳定技术降低了低频噪声和失调电压。电路采用标准CMOS工艺流片,测试结果显示,在5 V电源电压和250 kHz采样频率下,功耗约为20 mW;当过采样率为125时,不带斩波技术的调制器的SNR为89 dB,带斩波技术调制器的SNR为99 dB。通过对比测试,验证了设计思路的正确性。     

一种用于心电信号检测的低噪声斩波放大器

提出了一种适用于心电信号(ECG)检测的斩波调制放大器。基于现有的局部斩波调制放大器,采用全局斩波调制方式优化了电路噪声性能;采用正反馈阻抗提升技术显著提高了输入阻抗。首次提出了替代传统共源共栅结构的电流分裂式结构方案,有效降低了运放的基底噪声。采用TSMC 0.18 μm CMOS工艺对该放大器进行了仿真验证。结果表明,在1.8 V电源电压下,功耗仅为8.6 μW,在0.1~100 Hz范围内等效积分噪声为0.26 μV·Hz-1/2,输入阻抗为417 MΩ,共模抑制比达138 dB。     

一种单边输入阻抗可调的斩波放大器

提出了一种单边输入阻抗可调、无需纹波抑制的斩波放大器。通过单独调控电容耦合斩波放大器预充电时序,实现单边输入阻抗可调的放大器设计,这对于存在系统性源阻抗失配的信号检测是有意义的。同时还提出了一种高通型核心放大器,通过降低增益,达到了衰减因斩波调制引入的输出纹波的目的。因此,所提出的斩波放大器不再需要额外的纹波抑制电路。仿真结果显示,该斩波放大器具有61 MΩ~53 GΩ的直流单边输入阻抗可调范围,具有51.4 dB的纹波抑制能力。     

New topology for Class E amplifiers

A Class E RF amplifier, which can operate into any load conditions without need for other additional circuitry to protect transistors, is introduced. This is provided by the new topology, which is called an inductive clamp. Our topology incorporates inductive clamp circuitry to the basic Class E amplifier circuit and it has all the benefits of Class E amplifiers. Additionally, it has inherent self-protection that comes with the inductive clamp circuit. A Class E amplifier with the new topology is designed, simulated and implemented. The experimental results are presented and found to be very close to the simulated results. The amplifier drain efficiency is measured around 88% at the rated power level and it is confirmed that the amplifier protected itself and was stable over entire VSWR and dynamic range within the bandwidth of operational frequency. Class E amplifiers with this topology can be used in applications where the load conditions are dynamic.     

实用简易逻辑分析仪的设计与实现

介绍了基于示波器进行显示的简易逻辑分析仪的功能、系统组成和软硬件的设计方法,给出了详细的软件程序流程和硬件电路。该系统的控制部分采用单片机进行控制,输出电路采用由运算放大器构成的多踪显示电路设计,使电路结构简单,成本低。根据被测信号频率的高低,分别采用交替显示方式和断续显示方式,使高低频率的信号都能够稳定地显示,实用性强。     

基于∑-Δ调制的新型数字功率放大器设计

分析了二阶Σ-Δ调制技术的原理,设计了基于过采样、插值滤波和噪声整形技术、 Σ-Δ调制的数字D类功率放大器,并进行了建模仿真。仿真结果表明,设计的Σ-Δ调制数 字 功率放大器输出信噪比高,开关损耗小,整个系统工作频率低。Σ-Δ调制新型数字功率放 大器可以用低端硬件方便实现,有很好的应用价值。     

低噪声低功耗斩波运放的分析与设计

CMOS运放的噪声尤其是低频1/f噪声会随着整体功耗的降低而急剧增加,针对传感器读出电路应用,文中在传统斩波运放的基础上设计了一个低噪声、低功耗的嵌套式斩波运算放大器。基于SMIC0.18 μm工艺,通过Spectre仿真工具进行仿真与验证。高频斩波(fchop,high)频率为500 kHz,低频斩波频率(fchop,low)为2 kHz时的仿真结果表明,运放在100 Hz处的噪声功率谱密度(Power Spectral Density,PSD)降为23 nV[KF(]Hz[KF)],总消耗电流14 μA,放大器的增益带宽积(GBW)为16.7 MHz,运放的电流效率(GBW/Itot)达到了1 193,该设计的整体性能与以往的设计相比具有一定优势。     

Integrated CMOS amplifier for ENG signal recording

The development and in vivo test of a fully integrated differential CMOS amplifier, implemented with standard 0.7-microm CMOS technology (one poly, two metals, self aligned twin-well CMOS process) intended to record extracellular neural signals is described. In order to minimize the flicker noise generated by the CMOS circuitry, a chopper technique has been chosen. The fabricated amplifier has a gain of 74 dB, a bandwidth of 3 kHz, an input noise of 6.6 nV/(Hz)0.5, a power dissipation of 1.3 mW, and the active area is 2.7 mm2. An ac coupling has been used to adapt the electrode to the amplifier circuitry for the in vivo testing. Compound muscle action potentials, motor unit action potentials, and compound nerve action potentials have been recorded in acute experiments with rats, in order to validate the amplifier.     

Band-tunable and multiplexed integrated circuits for simultaneous recording and stimulation with microelectrode arrays

Two thin-film microelectrode arrays with integrated circuitry have been developed for extracellular neural recording in behaving animals. An eight-site probe for simultaneous neural recording and stimulation has been designed that includes on-chip amplifiers that can be individually bypassed, allowing direct access to the iridium sites for electrical stimulation. The on-probe amplifiers have a gain of 38.9 dB, an upper-cutoff frequency of 9.9 kHz, and an input-referred noise of 9.2 microV rms integrated from 100 Hz to 10 kHz. The low-frequency cutoff of the amplifier is tunable to allow the recording of field potentials and minimize stimulus artifact. The amplifier consumes 68 microW from +/- 1.5 V supplies and occupies 0.177 mm2 in 3 microm features. In vivo recordings have shown that the preamplifiers can record single-unit activity 1 ms after the onset of stimulation on sites as close as 20 microm to the stimulating electrode. A second neural recording array has been developed which multiplexes 32 neural signals onto four output data leads. Providing gain on this array eliminates the need for bulky headmounted circuitry and reduces motion artifacts. The time-division multiplexing circuitry has crosstalk between consecutive channels of less than 6% at a sample rate of 20 kHz per channel. Amplified, time-division-multiplexed multichannel neural recording allows the large-scale recording of neuronal activity in freely behaving small animals with minimum number of interconnect leads.     

Self-calibration of input-match in RF front-end circuitry

The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed technique ascertains the input match frequency of the circuit by using a built-in self-test (BiST) structure, determines the frequency interval by which it needs to be shifted to restore it to the desired value, and then feeds back a digital word to the low-noise amplifier (LNA), which adaptively corrects its input-match in real-time. The circuitry presented in the paper offers the advantages of low power overheads (the circuits can be powered off when not in use), robustness, no requirements of digital signal processing cores or processors, and fast calibration times (less than 30 /spl mu/s). This proof of concept is demonstrated by designing a cascode LNA and the complete self-calibration circuit in IBM 0.25-/spl mu/m CMOS RF process.     

2.5-THz GaAs monolithic membrane-diode mixer

A novel GaAs monolithic membrane-diode (MOMED) structure has been developed and implemented as a 2.5-THz Schottky diode mixer. The mixer blends conventional machined metallic waveguide with micromachined monolithic GaAs circuitry to form, for the first time, a robust, easily fabricated, and assembled room-temperature planar diode receiver at frequencies above 2 THz. Measurements of receiver performance, in air, yield at T_receiver of 16500-K double sideband (DSB) at 8.4-GHz intermediate frequency (IF) using a 150-K commercial Miteq amplifier. The receiver conversion loss (diplexer through IF amplifier input) measures 16.9 dB in air, yielding a derived “front-end” noise temperature below 9000-K DSB at 2514 GHz. Using a CO₂-pumped methanol far-infrared laser as a local oscillator at 2522 GHz, injected via a Martin-Puplett diplexer, the required power is ≈5 mW for optimum pumping and can be reduced to less than 3 mW with a 15% increase in receiver noise. Although demonstrated as a simple submillimeter-wave mixer, the all-GaAs membrane structure that has been developed is suited to a wide variety of low-loss high-frequency radio-frequency circuits     

A Novel On-Chip Amplifier for Fast I DD Current Monitoring

A novel circuit of the low-voltage application-specific amplifier is proposed and analyzed. A wide-band current amplifying cell is developed as a central part of the amplifier structure. The amplifier is designed for a built-in-current-sensor, on-chip circuitry used in high-frequency power supply current monitoring and test applications. It could be implemented with analog, digital, or mixed-signal cores in an integrated system-on-chip environment. The current amplifier has been fabricated in 0.13 and 0.18 μm CMOS technology processes with 1.2 and 1.8 V power supply, respectively. The impacts of technology scaling on amplifier's performances have been investigated as well. With sensitivity better than 500 nA, the 0.13 μm design achieves the gain-bandwidth product of 6.8 GHz, low frequency current gain of 48 dB, high linearity for the input current range of (?15 μA, 15 μA), and power consumption of 5.2 mW.     

A monolithic three-stage 2-8-GHz feedback amplifier

A monolithic three-stage resistive-feedback amplifier has been developed for the 2-8-GHz band. This amplifier uses a novel approach which incorporates three stages with varying FET gate widths. The measured gain is 19 ± 1 dB and the VSWR is 2.3:1 in this band. The amplifier chip has a noise figure of ∼6 dB over the bandwidth. The chip size is less than 2.0 × 1.6 mm²and includes the bias circuitry. The amplifier also has AGC capability with more than 20 dB of gain control.