Reactor characterization for a process to etchSi3N4 formed on thin SiO2

A plasma etching process for patterning LPCVD (low-pressure chemical vapor deposition) Si₃N₄ which has been formed on thin thermally grown SiO₂ has been developed and characterized with an Applied Materials 8110 batch system using 100-mm-diameter silicon wafers. To fulfill the primary process objectives of minimal critical dimension (CD) loss (~0.08 μm), vertical profiles after etch, retention of some of the underlying thermal SiO₂, and batch etch uniformity, the reactor has been characterized by evaluating the effects of variation of reactor pressure (15 to 65 mTorr), O₂ concentration by flow rate (30 to 70%) of an O₂/CHF₂ mixture, and DC bias voltage (-200 to -550 V). Analysis of the resulting etch rate, etch uniformity, dimensional, and profile data suggests that satisfactory processing may be achieved at low reactor pressure (~25 mTorr), 50-60% O₂ by flow rate in O₂/CHF₃, and low DC bias (-200 to -250 V)     

The degradation of TDDB characteristics of Si02/Si3N4/Si02 stacked films caused by surfaceroughness of Si3N4 films [DRAMs]

The effect of surface roughness of Si₃N₄ films on time-dependent dielectric breakdown (TDDB) characteristics of SiO₂/Si₃N₄/SiO₂ (ONO) stacked films was investigated. The surface roughness of Si₃N ₄ films-was found to become higher with increasing deposition temperature and to cause the degradation of TDDB characteristics of ONO films in DRAMs. A local thinning of ONO films, evaluated from the TDDB characteristics, agreed with the surface roughness measured by atomic force microscopy (AFM) and cross-sectional transmission electron microscopy (XTEM). Dependence of time to breakdown of ONO films on the deposition conditions was interpreted by electric field intensification due to the surface roughness of Si₃N₄ films     

Demonstration of Low-Leakage-Current Low-On-Resistance 600-V 5.5-A GaN/AlGaN HEMT

This letter demonstrates a high-voltage, high-current, and low-leakage-current GaN/AlGaN power HEMT with HfO₂ as the gate dielectric and passivation layer. The device is measured up to 600 V, and the maximum on-state drain current is higher than 5.5 A. Performance of small devices with HfO₂ and Si₃N₄ dielectrics is compared. The electric strength of gate dielectrics is measured for both HfO₂ and Si₃N₄. Devices with HfO₂ show better uniformity and lower leakage current than Si₃N₄ passivated devices. The 5.5-A HfO₂ devices demonstrate very low gate (41 nA/mm) and drain (430 nA/mm) leakage-current density and low on-resistance (6.2 Omegamiddotmm or 2.5 mOmegamiddotcm²).     

Formation of high quality storage capacitor dielectrics by in-siturapid thermal reoxidation of Si3N4 films inN2O ambient

This letter reports on a novel reoxidation technique for SiO₂ /Si₃N₄ (ON) stacked films by using N₂ O as oxidant. Effect of in-situ rapid thermal N₂O reoxidation (RTNO) on the electrical characteristics of thin ON stacked films are studied and compared with those of in-situ rapid thermal. O ₂ reoxidation (RTO). Prior to reoxidation, the Si₃N₄ film was deposited by rapid thermal chemical vapor deposition (RT-CVD) using SiH₄ and NH₃. Results show that RTNO of the Si₃N₄ films significantly improves electrical characteristics of ON stacked films in terms of lower leakage current, suppressed charge trapping, reduced defect density and improved time-dependent-dielectric-breakdown (TDDB), as compared to RTO of the Si₃N₄ films     

Ion implantation effects on GaAs MESFETs

The effects of ion-implantation on the uniformity and the ultimately achievable performance of GaAs MESFETs are calculated. The results of an extensive study of the profiles of Si, Se, and Be ions implanted into GaAs are incorporated into a combined process and device model for GaAs MESFET technology. Taken into account are the scaling of transconductances with implantation energy, effects of implant profiles and impurities on low-gate-bias transconductances, dopant diffusion during annealing, effects of encapsulant thickness and etch depth on threshold-voltage uniformity, and effects of recoil atoms on threshold voltages for implants through Si₃N₄ and SiO₂ caps     

Atomic layer deposited HfO/sub 2/in metal?insulator?metal capacitor for RF IC applications

DC and RF characteristics of Si/SiO₂(~4 mum)/Ti/Pt-HfO₂-Al metal-insulator-metal (MIM) devices were investigated with atomic layer-deposited (ALD) high-k HfO₂ films. Excellent DC and RF properties were obtained compared to those using either SiO₂ or Si₃N₄. Both high capacitance density and small frequency-dependent capacitance reduction were observed in the MIM capacitors, in which ALD HfO₂ was used as an insulator.     

Electrical characteristics of B-implanted p-channelMNOS transistors

Boron ions (¹¹B⁺ of 3·7 to 7·4 × 10¹¹/cm² were implanted at 60–120 keV into the channel region of p-channel MNOS double layer insulated gate field effect transistors through 920–940 Å of SiO₂ and various thicknesses (300–1800 Å) of Si₃N₄ deposited on SiO₂. Subsequent annealing was performed in a nitrogen atmosphere at 1000°C for 30 min. Acceleration energy, implant dose and Si₃N₄ thickness dependences of the shift of the threshold voltage showed good agreement with the calculated results based on Ishiwara and Furukawa's theory for distribution of implanted atoms in the double layered substrate, using the projected ranges and standard deviations larger than LSS predictions by the factor of 1·2 for SiO₂ and 1·3 for Si₃N₄, respectively. The results on the gain terms and the breakdown voltages were qualitatively the same as those of ¹¹B⁺-implanted p-channel MOS transistors.     

Avalanche electron injection in 4-nmSi3N4/8-nm SiO2 dielectric structure:turn-around phenomenon and Si-SiO2 interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si₃N₄+8-nm SiO₂) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si₃N₄ interface) and subsequent trapping near the SiO₂-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO₂-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping     

A Short-Channel SOI RF Power LDMOS Technology With$hboxTiSi_2$Salicide on Dual Sidewalls With Cutoff Frequency$f_T sim hbox19.3 hboxGHz$

In this letter, a CMOS-compatible silicon-on-insulator (SOI) RF laterally diffused MOS (LDMOS) technology is proposed based on TiSi₂ salicide with SiO₂/Si₃N₄ dual sidewalls. The use of dual sidewalls yields a large process margin for defining drift regions and preventing source-gate silicide bridging. This technology improves the cutoff frequencies and the maximum oscillation frequencies by 27%-42% and 14%-22%, respectively, for a gate length in the range of 0.5-0.25 mum. For the shortest 0.25-mum gate length, a record cutoff frequency of 19.3 GHz and a high breakdown voltage of 16.3 V are achieved simultaneously for SOI RF LDMOS. This LDMOS technology is suitable for 3.6-V-supply 0-3-GHz power RFIC applications     

Electrical Characteristics of Memory Devices With a High- k HfO2 Trapping Layer and Dual SiO2/Si3N4 Tunneling Layer

A novel device structure with a high-k HfO₂ charge storage layer and dual tunneling layer (DTL) (SiO₂/Si₃N₄) is presented in this paper. Combining advantages of the high trapping efficiency of high-k materials and enhanced charge injection from the substrate through the DTL, the device achieves a fast program/erase speed and a large memory window. The device demonstrates excellent retention due to its physically thick DTL and also improved endurance without any increase of programming V_th throughout the cyclic test as compared with SONOS Flash memory devices using an Si₃N₄ trapping layer.     

Performance and hot-carrier reliability of 100 nm channel lengthjet vapor deposited Si3N4 MNSFETs

Metal-nitride-semiconductor FETs (MNSFETs) having channel lengths down to 100 mm and a novel jet vapor deposited (JVD) Si₃N₄ gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO₂ gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si₃N₄ barrier (2.1 eV) is lower than the Si-SiO₂ barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO₂ MOSFETs     

Formation of high quality ultrathin oxide/nitride (ON) stackedcapacitors by in situ multiple rapid thermal processing [DRAMcells]

High quality, ultrathin (<30 Å) SiO₂/Si₃ N₄ (ON) stacked film capacitors have been fabricated by in situ rapid-thermal multiprocessing. Si₃N₄ film was deposited on the RTN-treated poly-Si by rapid-thermal chemical vapor deposition (RTCVD) using SiH₄ and NH₃, followed by in situ low pressure rapid-thermal reoxidation in N₂O (LRTNO) or in O₂ (LRTO) ambient. While the use of low pressure reoxidation suppresses severe oxidation of ultrathin Si₃N₄ film, the use of N₂O-reoxidation significantly improves the quality of ON stacked film, resulting in ultrathin ON stacked film capacitors with excellent electrical properties and reliability     

High efficiency polycrystalline silicon solar cells using lowtemperature PECVD process

Conventionally directionally solidified (DS) and silicon film (SF) polycrystalline silicon solar cells are fabricated using gettering and low temperature plasma enhanced chemical vapor deposition (PECVD) passivation. Thin layer (~10 nm) of PECVD SiO₂ is used to passivate the emitter of the solar cell, while direct hydrogen rf plasma and PECVD silicon nitride (Si₃N₄) are implemented to provide emitter and bulk passivation. It is found in this work that hydrogen rf plasma can significantly improve the solar cell blue and long wavelength responses when it is performed through a thin layer of PECVD Si₃N₄. High efficiency DS and SF polycrystalline silicon solar cells have been achieved using a simple solar cell process with uniform emitter, Al/POCl₃ gettering, hydrogen rf plasma/PECVD Si₃N₄ and PECVD SiO₂ passivation. On the other hand, a comprehensive experimental study of the characteristics of the PECVD Si₃N₄ layer and its role in improving the efficiency of polycrystalline silicon solar cells is carried out in this paper. For the polycrystalline silicon used in this investigation, it is found that the PECVD Si₃N₄ layer doesn't provide a sufficient cap for the out diffusion of hydrogen at temperatures higher than 500°C. Low temperature (⩽400°C) annealing of the PECVD Si₃N ₄ provides efficient hydrogen bulk passivation, while higher temperature annealing relaxes the deposition induced stress and improves mainly the short wavelength (blue) response of the solar cells     

Oxidized Ta2O5/Si3N4dielectric films on poly-crystalline Si for dRAMs

A dielectric film technology characterized by a novel multilayer structure formed by oxidation of Ta₂O₅/Si₃ N₄ films on polysilicon has been developed to realize high-density dRAMs. The dry oxidation of the Ta₂O₅/Si₃N₄ layers was performed at temperatures higher than 900°C. This film has a capacitance per unit area from 5.5 to 6.0 fF/ μm², which is equivalent to that of a 6.0- to 6.5-nm-thick SiO₂. The leakage current at an effective electric field of 5 MV/cm is less than 10^-9 A/cm². Under such an electric field, the extrapolated time to failure for 50% cumulative failure can be as high as 1000 years     

Enhanced H2-plasma effects on polysilicon thin-filmtransistors with thin ONO gate-dielectrics

This letter reports that passivation effects of the H₂-plasma on the polysilicon thin-film transistors (TFT's) were greatly enhanced if the TFT's have a thin Si₃N₄ film on their gate-dielectrics. Compared to the conventional devices with only the SiO₂ gate dielectric, the TFT's with Si ₃N₄ have much more improvement on their subthreshold swing and field-effect mobility after H₂-plasma treatment     

Design optimization of stacked layer dielectrics for minimum gate leakage currents

An effective model to evaluate the leakage currents for different stacked gates deep submicron MOS transistors is presented. For a given equivalent oxide thickness of a stacked gate, the gate leakage current decreases with an increase of high-k dielectric thickness or a decrease of interlayer thickness. Turning points at high gate biases of the I–V curves are observed for Si₃N₄/SiO₂, Ta₂O₅/SiO₂, Ta₂O₅/SiO_2−yN_y, Ta₂O₅/Si₃N₄, and TiO₂/SiO₂ stacked gates except for Al₂O₃/SiO₂ structure. Design optimization for the stacked gate architecture to obtain the minimum gate leakage current is evaluated.     

Enhanced corrugated QWIP performance using dielectric coverage

We report here the effect of dielectric/metal coverage on the performance of the corrugated quantum well infrared photodetectors (C-QWIP) in two wavelength regimes. We found that with proper dielectrics, both the detector dark current and the spectral responsivity can he improved upon the monitoring 45° edge coupled QWIP. In the 8 μm regime, the normalized responsivity of a Si₃ N₄ covered C-QWIP was found to be improved by 3.3 times. In the 14 μm regime, the improvement is a factor of 1.8 using Si₃N₄ coverage and a factor of 2.5 using SiO₂ coverage     

From diffusion processes to adherence properties in NiTi microactuators

Diffusion processes taking place at the NiTi/Si, NiTi/SiO₂ and NiTi/Si₃N₄ interfaces under annealing are studied in order to understand the adherence properties of these systems after annealing. Secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS) assisted by argon etching and electron-induced X-ray emission spectroscopy (EXES) are combined in order to analyse at a nanometric scale the interfaces before and after annealing. Considerable differences between diffusion processes in NiTi/Si and NiTi/SiO₂ are observed and can explain the difference between adherence properties of these systems after annealing. Among the three studied systems, NiTi/Si₃N₄ is shown to be the most suited for low voltage microactuation applications.     

氮化硅集成微腔光频梳器件关键制备技术(特邀)

微腔光频梳,又称微腔梳,是通过腔内四波混频过程产生的一种高相干宽谱的集成光源,有着优异的时频特性,可用于超精密分子光谱、相干通信、激光雷达、轻型化装备等测量应用,是基础科学、计量学及军事装备的重要工具,是一项颠覆性的技术。报道了一种集成氮化硅（Si₃N₄）微腔光频梳器件制备的关键技术,提出了一种方法平衡Si₃N₄的应力、厚度和化学计量之间的矛盾,以满足反常色散和减少双光子吸收的要求。利用这种改进的大马士革工艺微结构降低Si₃N₄厚膜的应力,减少应力缺陷对器件性能的影响,实现高品质Si₃N₄薄膜的可控制备。在微腔刻蚀工艺中,采用30 nm氧化铝牺牲层补偿掩模抗刻蚀能力,实现微环和波导侧壁粗糙度小于15 nm,满足了微腔高Q值的要求。经双光泵浦测量得到1 480~1 640 nm波段内的宽光谱高相干克尔光频梳。     

Fabrication of a 100%fill-factor silicon microlens array

正A simple method has been developed for the fabrication of a silicon microlens array with a 100%fill factor and a smooth configuration.The microlens array is fabricated by using the processes of photoresist(SU8- 2005) spin coating,thermal reflow,thermal treatment and reactive ion etching(RIE).First,a photoresist microlens array on a single-polished silicon substrate is fabricated by both thermal reflow and thermal treatment technologies. A typical microlens has a square bottom with size of 25μm,and the distance between every two adjacent microlenses is 5μm.Secondly,the photoresist microlens array is transferred to the silicon substrate by RIE to fabricate the silicon microlens array.Experimental results reveal that the silicon microlens array could be formed by adjusting the quantities of the reactive ion gases of SF_6 and O_2 to proper values.In this paper,the quantities of SF_6 and O_2 are 60 sccm and 50 sccm,respectively,the corresponding etch ratio of the photoresist and the silicon substrate is 1 to 1.44.The bottom size and height of a typical silicon microlens are 30.1μm and 3μm,respectively. The focal lengths of the microlenses ranged from 15.4 to 16.6μm.