一种1GHz多频带压控振荡器的设计

基于3.3V 0.35μm TSMC 2P4M CMOS体硅工艺,设计了一款1GHz多频带数模混合压控振荡器.采用环形振荡器加上数模转换器结构,控制流入压控振荡器的电流来调节压控振荡器的频率而实现频带切换.仿真结果表明,在1V～2V的电压调节范围内,压控振荡器输出频率范围为823.3MHz～1.061GHz,且压控振荡器的增益仅有36.6MHz/V,振荡频率为1.0612GHz时,频率偏差1MHz处的相位噪声为-96.35dBc/Hz,在获得较大频率调节范围的同时也能保持很低的增益,从而提高了压控振荡器的噪声性能.     

适用于万兆以太网10GBASE􀀂X 的全集成单片CMOS 压控振荡器

给出了一个适用于万兆以太网IEEE80 2 3ae 10GBASE -X的高线性度全集成单片环形压控振荡器电路。该压控振荡器采用TSMC 0 18μmCMOS混合信号工艺设计制造 ,由四级差分延时单元和输出驱动电路组成 ,芯片总面积为 0 3× 0 4mm2 。芯片采用 1 8V单电源供电 ,测得带直接耦合差分 5 0Ω负载时的总功耗为 78mW ,单端输出功率为 10 2dBm ,振荡频率在 2 8～ 4 0GHz有非常好的压控线性度 ,在振荡器中心频率为 3 12 5GHz时的单边带相位噪声为 - 96dBc/Hz@10MHz。     

振荡型有源集成天线

研制中心频率为18 GHz的振荡型有源集成天线,包括微带天线设计、单片压控振荡器(MMIC VCO)的设计及微带天线与单片压控振荡器二者的集成。微带天线的芯片面积为4.5 mm×3.5 mm,增益为3.67 dB,中心频率为18.032 GHz,最小输入驻波系数为1.098;单片压控振荡器芯片面积1.1 mm×1.0 mm,调谐范围为15.978～18.247 GHz,输出功率大于6 dBm。振荡型有源集成天线的方向图测试结果与微带天线的特性符合,该振荡型有源集成天线能够正常工作。     

一种宽带低相噪CMOS LC压控振荡器设计

设计了一种频率可调范围约830MHz全集成CMOS LC压控振荡器.该压控振荡器利用了一种改进的四位二进制加权的开关电容阵列扩大了其调谐范围;采用了可变尾电流源设计,使得振荡信号在整个频率范围内幅度变化不大.结果表明,该压控振荡器总调节范围1.12～1.95GHz,功耗为6.5～19.1mW,采用0.35μm CMOS RF工艺设计版图面积为360μm×830μm,工作于1.1GHz和1.9GHz时,1MHz频偏处的单边带相位噪声分别为-122dBc/ Hz、-120dBc/ Hz.     

多输出时钟发生器

AD9520与AD9522多输出时钟发生器内置一个512Byte的嵌入式EEPROM存储器模块、分频器、扇出缓冲器，以及振荡范围为1．4～2．95GHz的VCO（压控振荡器）。其还可以使用振荡频率高达2．4GHZ的外部3．3V／5VVCO／VCXO（压控晶体振荡器）。     

一种低噪声C类LC压控振荡器的设计

为了改善压控振荡器相位噪声,基于40 nm CMOS工艺,设计一种低噪声C类LC压控振荡器。交叉耦合NMOS对管通过电流镜偏置作为电路的电流源,并采用共模反馈偏置电路使交叉耦合PMOS对管工作在饱和区,保证LC压控振荡器实现C类振荡。通过差分可变电容的设计,压控振荡器的增益减小,压控振荡器的相位噪声得到改善。设计了4组开关电容进行调节,增大压控振荡器的调谐范围。仿真结果表明,处于1.2 V的电压下,压控振荡器振荡频率范围在4.14～5.7 GHz,频率调谐范围变化率达到31.2%,相位噪声为-112.8 dBc/Hz。     

低功耗CMOS差分环形压控振荡器设计

提出了一个基于0.18μm标准CMOS工艺实现的四级差分环形压控振荡器.全差分环形压控振荡器采用带对称负载的差分延时单元.仿真结果表明,压控振荡器的频率范围在最坏情况为0.21～1.18GHz;偏离中心频率10MHz情况下,压控振荡器的相位噪声为-118.13dBc/Hz; 1.8V电源电压下,中心频率为600MHz时,压控振荡器的功耗仅有4.16mW;版图面积约为0.006mm2.可应用于锁相环和频率综合器设计中.     

应用于IMT-A和UWB系统的0.13μm CMOS宽带压控振荡器设计

基于TSMC 0.13μm CMOS工艺设计并实现了应用于IMT-Advanced和UWB系统的双频段宽带频率合成器中的电感电容压控振荡器(LC-VCO)。此压控振荡器的设计采用了开关电流源、开关交叉耦合对和噪声滤波等技术,以优化电路的相位噪声,功耗,振荡幅度,调谐范围等性能。为达到宽的调谐范围,核心电路采用了4比特可重构的开关电容调谐阵列。整个芯片包括焊盘面积为1.11′0.98 mm₂。测试结果表明,在1.2V电源电压下,两个频段压控振荡器所消耗的电流分别为3mA和4.5mA,压控振荡器的调谐范围为3.86~5.28GHz和3.14~3.88GHz。在振荡频率3.5GHz和4.2GHz上,1MHz频偏处,压控振荡器的相位噪声分别为-123dBc/Hz与-119dBc/Hz。     

快速建立振荡的低噪声Ku波段基频双极压控振荡器

本文讨论在Ku波段(15～18GHz和12～15GHz)上快速建立振荡的基频输出压控振荡器,它是用硅双极晶体管和硅变容二极管构成。这些振荡器输出频率建立时间在2μs以内,最终频率在±1MHz范围内。在载波100kHz频率跨度、16.2GHz下测得相位噪声为-93dBc/Hz。     

压控振荡器在射频通信电路中的应用

随着现代通信系统和现代雷达系统的出现,射频电路需要在特定的载波频率点上建立稳定的谐波振荡,以便为调制和混额创造必要的条件.设计了一个振荡频率在1.14～1.18 GHz的负阻LC压控振荡器,实现了压控振荡器的宽调频,使频率范围达到加MHz.并且为避免在外部电路对压控振荡器(VCO)的影响,在电路中加入射极跟随器作为buffer,起到阻抗变换和级间隔离的作用.为负阻LC压控振荡器的设计提供了一种参考电路.     

一种用于短距离器件的带自校准的∑-Δ分数分频频率综合器

介绍了一种应用于433/868MHz频段短距离器件的分数分频频率综合器.采用带自适应频率校准的宽带压控振荡器来覆盖要求的频段,并采用3位量化、3阶的Σ△调制器来实现分数分频和改善锁相环的带外噪声.测试结果表明,自适应频率校准能够正常工作,压控振荡器的频率调节范围为1.31～1.18GHz,在3MHz频偏处的带外噪声为-139dBc/Hz,分数毛刺低于-60dBc.芯片采用0.35μm CMOS工艺,芯片面积仅为1.8mm2,功耗仅为57mW.     

一种用于短距离器件的带自校准的∑-Δ分数分频频率综合器

介绍了一种应用于433/868MHz频段短距离器件的分数分频频率综合器.采用带自适应频率校准的宽带压控振荡器来覆盖要求的频段,并采用3位量化、3阶的Σ△调制器来实现分数分频和改善锁相环的带外噪声.测试结果表明,自适应频率校准能够正常工作,压控振荡器的频率调节范围为1.31～1.18GHz,在3MHz频偏处的带外噪声为-139dBc/Hz,分数毛刺低于-60dBc.芯片采用0.35μm CMOS工艺,芯片面积仅为1.8mm2,功耗仅为57mW.     

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW.     

A K-band InGaP/GaAs HBT balanced MMIC VCO

A fully integrated K-band balanced voltage controlled oscillator (VCO) is presented. The VCO is realized using a commercially available InGaP/GaAs heterojunction bipolar transistor (HBT) technology with an f/sub T/ of 60 GHz and an f/sub MAX/ of 110 GHz. To generate negative resistance at mm-wave frequencies, common base inductive feedback topology is used. The VCO provides an oscillation frequency from 21.90 GHz to 22.33 GHz. The frequency tuning range is about 430 MHz. The peak output power is -0.3 dBm. The phase noise is -108.2 dBc/Hz at 1 MHz offset at an operating frequency of 22.33 GHz. The chip area is 0.84/spl times/1.00 mm/sup 2/.     

一种带有升压电路的0.5V 3GHz低功耗LC VCO设计

采用标准的0.13μm CMOS工艺实现了0.5V电源电压,3GHz LC压控振荡器。为了适应低电压工作,并实现低相位噪声,该压控振荡器采用了NMOS差分对的电压偏置振荡器结构,去除尾电流,以尾电感代替,采用感性压控端,增加升压电路结构使变容管的一端升压,这样控制电压变化范围得到扩展。测试结果显示,当电源电压为0.5V,振荡频率为3.126GHz时,在相位噪声为-113.83dBc/Hz@1MHz,调谐范围为12%,核心电路功耗仅1.765mW,该振荡器的归一化品质因数可达-186.2dB,芯片面积为0.96mm×0.9mm。     

A 15-GHz monolithic low-phase-noise VCO using AlGaAs/GaAs HBTtechnology

A 15-GHz fully monolithic low-phase-noise VCO MMIC fabricated without an external tuning element using an AlGaAs/GaAs HBT technology was developed. An HBT and a variable capacitance diode or varactor were fabricated in an MMIC chip using-standard HBT IC process. A tuning range of about 600 MHz was obtained with varying control voltage from 0 to 4 V with an output power of more than -4 dBm. The low phase noise for an offset frequency of 100 kHz of -85 dBc/Hz was measured at a frequency of 15.6 GHz     

具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

A 0.7 V 6.66–9.36 GHz wide tuning range CMOS LC VCO with small chip size

The circuit designs are based on TSMC 0.18 μm CMOS standard technology model. The designed circuit uses transformer coupling technology in order to decrease chip area and increase the Q value. The switched-capacitor topology array enables the voltage-controlled oscillator (VCO) to be tuned between 6.66 and 9.36 GHz with 4.9 mW power consumption at supply voltage of 0.7 V, and the tuning range of the circuit can reach 33.7%. The measured phase noise is ?110.5 dBc/Hz at 1 MHz offset from the carrier frequency of 7.113 GHz. The output power level is about ?1.22 dBm. The figure-of-merit and figure-of-merit-with-tuning range of the VCO are about ?180.7 and ?191.25 dBc/Hz, respectively. The chip area is 0.429 mm² excluding the pads. The presented ultra-wideband VCO leads to a better performance in terms of power consumption, tuning range, chip size and output power level for low supply voltage.     

A 1-V 9.7-mW CMOS Frequency Synthesizer for IEEE 802.11a Transceivers

A 1-V CMOS frequency synthesizer is proposed for wireless local area network 802.11a transceivers using a novel transformer-feedback voltage-controlled oscillator (VCO) for low voltage and a stacked frequency divider for low power. Implemented in a 0.18-mum CMOS process and operated at 1-V supply, the VCO measures a phase noise of -140.5 dBc at an offset of 20 MHz with a center frequency of 4.26 GHz and a power consumption of 5.17 mW. Its tuning range is as wide as 920 MHz (23%). By integrating the VCO into a frequency synthesizer, a phase noise of -140.1 dBc/Hz at an offset of 20 MHz is measured at a center frequency of 4.26 GHz. Its output frequency can be changed from 4.112 to 4.352 GHz by switching the 3-bit modulus of the programmable divider. The synthesizer consumes only 9.7 mW and occupies a chip area of 1.28 mm².