一种具有瞬态增强的无片外电容型LDO

提出了一种稳定性高、瞬态特性良好、无片外电容的低压差线性稳压器(LDO)。采用推挽式微分器检测负载瞬态变化引起的输出电压变化,加大对功率管栅极寄生电容的充放电电流,增强系统的瞬态响应能力;在误差放大器后接入缓冲级,将功率管栅极极点推向高频,并采用密勒电容进行频率补偿,使系统在全负载范围内稳定。基于TSMC 65 nm CMOS工艺进行流片,核心电路面积为0.035 mm²。测试结果表明,最低供电电压为1.1 V时,压降仅为100 mV,负载电流1 μs内在1 mA和150 mA之间跳变时,LDO的最大输出过冲电压与下冲电压分别为200 mV和180 mV。     

一种衬底波纹注入的宽频带高PSR无片外电容LDO

基于40 nm CMOS工艺,设计了一种具有高频高电源抑制(PSR)的无片外电容 低压差线性稳压器(LDO)电路。电路采用1.1 V电源供电,LDO输出电压稳定在0.9 V。仿真结果表明,传统无片外电容LDO电路的PSR将会在环路的单位增益 频率(UGF)处上升到一个尖峰,之后才经输出节点处的电容到地的通路开始降低,最高时PSR甚至大于0 dB。采用新型的衬底波纹注入技术的LDO能很好地抑制PSR的尖峰,可以做到全频段都在-20 dB以上,相比传统结构,尖峰处的PSR提高了20 dB以上。该LDO适用于需要低电压供电的射频电路。     

基于高压摆率误差放大器和摆率增强电路的无片外电容LDO

基于0.35μm CMOS工艺设计了一款无片外电容低压差线性稳压器(cap-free LDO),通过误差放大器组成的环路控制稳态误差,通过摆率增强电路构成的环路改善瞬态响应。该LDO输出电压为1.72V,压差80mV,最大输出电流50mA。测试结果显示:负载电流(IL)在0.5μs内瞬变50mA时,俯冲电压和过冲电压均为80mV左右,重回稳态的时间均小于1.5μs。     

一种快速瞬态响应的无片外电容LDO

设计了一种快速瞬态响应的无片外电容低压差线性稳压器(LDO)。采用具有摆率增强作用的缓冲级电路,可以在不额外增加静态电流的同时检测输出端电压,在负载瞬间变化时增大功率器件栅极电容的充放电电流。缓冲级电路还引入了简单的负反馈技术,增加了环路的相位裕度。采用SMIC 180 nm的CMOS工艺进行设计和仿真。仿真结果表明,当输入电压为1.4~5 V时,该LDO的输出电压为1.2 V,最大负载电流为300 mA; 负载电流在1 mA和300 mA间变化时,最大过冲电压为76.5 mV,响应时间仅为1.5 μs。     

一种快速瞬态响应无片外电容LDO

针对无片外电容LDO,在误差放大器与功率管之间添加缓冲器,采用频率补偿的方法,提高了环路稳定性。通过检测负载瞬态变化引起的误差放大器输出电压变化,增加对功率管栅极电容的充放电电流,提升了系统的快速瞬态响应能力。基于TSMC 0.18 μm标准CMOS工艺,设计了一种输入电压范围为1.92~3.60 V、输出电压为1.8 V的LDO。结果表明,负载在1 μs内从0变化到100 mA时,输出最大下冲电压为37.2 mV,响应时间为1.12 μs;负载在1 μs内从100 mA变化到0时,输出最大过冲电压为40.1 mV,响应时间为1.1 μs。     

一种无片外电容高瞬态响应LDO设计

针对SoC中电源管理模块对高功能-面积比和高瞬态响应的需求,本文提出一种基于翻转电压跟随器（FVF）的无片外电容低压差线性稳压器（LDO）,采用电压峰值检测技术实现动态电流偏置,进而提升系统瞬态响应。基于SMIC 40nm工艺的仿真结果表明,在典型负载切换状态下,提出方案的下冲和上冲恢复时间相比传统的FVF结构LDO电路分别缩短了75%和29%。     

一种低功耗无片外电容LDO的设计

基于SMIC 0.18 μm CMOS工艺,设计了一款输入电压为1.8 V、输出电压为1.6 V的低功耗无片外电容低压差线性稳压器(LDO),其静态电流仅为5 μA。该电路采用一种新型摆率增强电路,通过检测输出电压的变化实现对功率管的瞬态调节。片内采用密勒补偿使主次极点分离,整个系统在负载范围内具有良好的稳定性。仿真结果显示,该LDO在负载电流以99 mA/1 μs跳变时,输出电压下冲为59 mV,上冲为60 mV,响应时间约为1.7 μs。     

高稳定性无片外电容低压差线性稳压器的设计

设计了一款无片外电容低压差线性稳压器(LDO),与传统的LDO相比,此LDO消除了传统结构中所需的片外电容,可更好地应用于全集成低功耗的片上系统(SoC)中。针对无片外电容LDO没有外部等效零点补偿这一特点,采用一种折叠输入推挽输出误差放大器结构,结合密勒补偿以及一阶RC串联零点补偿两种方案,有效地改善了无片外电容LDO的稳定性。电路采用SMIC0.18μm CMOS工艺实现,面积为0.11 mm2,最大负载电容100 pF,输入电压为1.8 V时,输出电压为1.5 V,静态电流31.8μA,压差为160 mV。     

一种无片外电容LDO的稳定性分析

电路如果存在不稳定性因素,就有可能出现振荡。本文对比分析了传统LDO和无片电容LDO的零极点,运用电流缓冲器频率补偿设计了一款无片外电容LDO,电流缓冲器频率补偿不仅可减小片上补偿电容而且可以增加带宽。对理论分析结果在Cadence平台基上于CSMC0.5um工艺对电路进行了仿真验证。本文无片外电容LDO的片上补偿电容仅为3pF,减小了制造成本。它的电源电压为3.5～6 V,输出电压为3.5 V。当在输入电源电压6 V时输出电流从100μA到100mA变化时,最小相位裕度为830,最小带宽为4.58 MHz     

基于高摆率误差放大器的无片外电容LDO设计

为了解决无片外电容低压差线性稳压器(LDO)的瞬态响应性能较差的问题,采用跨导提高技术设计了一种高摆率的误差放大器.在误差放大器的基础上,通过电容将LDO的输出端耦合至电流镜构建瞬态增强电路,提升LDO的瞬态响应能力,且瞬态增强电路可以引入两个左半平面零点,改善环路的稳定性.同时,误差放大器采用动态偏置结构,进一步减小...     

一种适用于SoC的瞬态增强型线性稳压器

为满足SoC系统负载快速变化的要求,提出了一种新型摆率增强型片上LDO系统。通过增加有效的内部检测电路,使LDO的功率管栅极电压可以快速地响应输出负载跳变,提高电路响应速度。采用中芯国际40 nm CMOS工艺模型,对电路进行仿真。仿真结果表明,当LDO的负载电流以100 mA/μs跳变时,电路的最大上冲电压为110 mV,下冲电压为230 mV,恢复时间分别为1.45 μs和1.6 μs。同时,在2 V电源电压下,电路的静态电流只有42 μA。     

A high-PSR transient-enhanced output-capacitorless CMOS low-dropout regulator for SoC applications

A transient-enhanced output-capacitorless CMOS low-dropout voltage regulator (LDO) with high power supply rejection (PSR) is introduced for system-on-chip applications. In order to reduce external pin count and device area and be amenable to full integration, the large external capacitor used in the classical LDO design is eliminated and replaced with a much smaller 5.7?pF on-chip capacitor. High-gain folded-cascode stage, wideband common source stage, voltage subtractor stage and transient-enhanced circuit are designed altogether to realise circuit compensation and achieve good frequency and transient performances. A current-sensing and transient-enhanced circuit is utilised to reduce transient voltage dips effectively and efficiently drive different kinds of load capacitances. The active chip area of the proposed regulator is only 200?×?280?µm². The simulation results under mixed-signal 0.18?µm 1P6M process show that this novel LDO's output voltage can recover within 1.7?µs (rising) and 2.41?µs (falling) under full load-current changes. The input voltage is ranged from 2 to 5?V for a load current 50?mA and an output voltage of 1.8?V. This novel LDO has wide unity-gain frequency stability and is stable for estimated equivalent parasitic capacitive loads from 0 to 100?pF. Moreover, it can achieve a PSR of ?78.5 and ?73?dB at 1 and 10?kHz, respectively.     

用于低压差线性稳压器的输出精密微调设计技术

提出了一种用于低压差线性稳压器(LDO:Low-Dropout regulator)的输出精密微调方法,通过在反馈网络中引入可微调电阻梯实现对LDO输出的精密调整,并采取伪电阻保护的版图布局方式提高电阻梯的匹配性能。基于65 nm CMOS工艺对LDO进行了设计,整个LDO线性调整率约为0.05mV/V,输出电压在1.02V~1.36V范围内能够按照0.02V/step的最小步长进行精密微调,能有效减小由电源电压、温度等因素引起的输出误差,适合嵌入式片上系统(So C:System-on-Chip)的应用。     

一种应用于SoC的小面积LDO设计

通过对LDO降压转换器的原理分析,对其稳定性和频率响应进行深入的研究,通过电路的小信号模型分析,抽取传输函数,并运用极坐标法对运放的零极点进行了分析．利用调整运放内部器件参数的方法使零点与板点发生变化,从而在不采用电容进行外部补偿的前提下,减小了芯片面积。提高了系统稳定性,设计的相位裕度大于60°,单位增益频率为322kHz,直流增益为60dB左右,静态电流在50uA左右的LDO降压转换器。这里针对特定SoC的低电压供电要求,从应用出发设计了不需要电容补偿的小面积LDO降压转换器。     

A 200 mA CMOS low-dropout regulator with double frequency compensation techniques for SoC applications

This paper presents a 200 mA low-dropout(LDO) linear regulator using two modified techniques for frequency compensation.One technique is that the error amplifier uses a common source stage with variable load, which is controlled by the output current,is served as the second stage for a stable frequency response.The other technique is that the LDO uses a pole-zero tracking compensation technique at the error amplifier to achieve a good frequency response.The proposed circuit was fabricated and tested in HJTC 0.18μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8-5 V and provides up to 200 mA load current for an output voltage of 1.8 V.The total error of the output voltage due to line and load variation is less than 0.015%.The LDO die area is 630×550μm~2 and the quiescent current is 130μA.     

A 200 mA CMOS low-dropout regulator with double frequency compensation techniques for SoC applications

This paper presents a 200mA low-dropout (LDO) linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier using common source stage with variable load, which is controlled by output current, is served as the second stage for stable frequency responses. Another technique is the LDO uses pole-zero tracking compensation technique at error amplifier to achieve good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8V-5V and provides up to 200mA load current for an output voltage of 1.8V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630*550μm² and the quiescent current is 130μA.     

A hybrid NMOS/PMOS capacitor-less low-dropout regulator with fast transient response for SoC applications

In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time about 680 nsec. It can supply current from 10 µA to 100 mA consuming quiescent current of 20.5 µA and 95 µA, respectively. It supports load capacitance from 0 to 50 pF with phase margin that increases from 43° at low load (10 µA) to 74° at high load (100 mA) and power supply rejection ratio (PSRR) less than −20 dB up to 100 kHz. The proposed LDO is designed in 130 nm CMOS technology and occupies an area of 0.11 mm². Post layout simulations show better performance compared with other reported techniques.     

一种用于大功率音频功放的高稳定性LDO

设计了一种用于大功率音频功放的高稳定性低压差线性稳压器(LDO),对其电路结构和工作原理进行了分析,重点讨论了上电预充模块、环路稳定性及电源抑制能力。采用0.18μm 1P4M BCDMOS工艺,不同工艺角下,Cadence Spectre仿真表明,LDO的温度系数小于47.45 ppm/℃,瞬态响应最大变化量为50 mV,电源抑制大于71 dB@1 kHz,工作电压范围5 V~24 V,输出电压值为3.3 V;tt(渡越时间)模型下,工作电压为18 V 时,对大功率音频功放进行系统仿真,LDO 表现出约为30μs的启动时间,其输出电压值能很好地跟踪负载电流的变化。     

A digitally controlled PLL for SoC applications

A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. The design is, therefore, portable between technologies as an IP block. Using a 0.35-/spl mu/m standard CMOS process and a 3.0-V supply voltage, the PLL has a frequency range of 152 to 366 MHz and occupies an on-chip area of 0.07 mm/sup 2/. In addition, the next version of this all-digital PLL is described in synthesizable VHDL code, which simplifies digital system simulation and change of process. A new time-to-digital converter with higher resolution is designed for the improved PLL. An improved digitally controlled oscillator is also suggested.