共查询到20条相似文献,搜索用时 15 毫秒
1.
《Lightwave Technology, Journal of》2009,27(3):177-188
2.
Yu J.. Xu L.. Ji P.N. Jia Z.. Yang Q.. Wang T.. Chang G.-K.. 《Photonics Technology Letters, IEEE》2007,19(17):1310-1312
We have experimentally demonstrated how to generate 100-Gb/s packet signals with spectral efficiency higher than 1bit/Hz/s for the first time. The optical packet with 3.125-Gb/s label and 100-Gb/s return-to-zero differential quadrature phase-shift-keying payload are generated by using optical carrier-suppression and separation and vestigial sideband filtering techniques. The performance of transmission and label erasure has also been evaluated. 相似文献
3.
Gripp J. Winzer P.J. Raybon G. Simsarian J.E. Doerr C.R. 《Photonics Technology Letters, IEEE》2007,19(15):1124-1126
We demonstrate 107-Gb/s optical packet switching using electronically multiplexed duobinary signals, fast tunable lasers, and a 40 times 40 arrayed waveguide grating router. With a spectral efficiency of 1 bit/s/Hz, the fabric scales to 4-Tb/s capacity and is suitable for 100-Gb Ethernet backplanes. 相似文献
4.
Sano K. Murata K. Sugitani S. Sugahara H. Enoki T. 《Solid-State Circuits, IEEE Journal of》2003,38(9):1504-1511
A 50-Gb/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) chip set using InP high electron mobility transistors (HEMTs) is described. In order to achieve wide-range bit-rate operation from several to 50 Gb/s, timing design inside the ICs was precisely executed. The packaged MUX operated from 4 to 50Gb/s with >1-V/sub pp/ output amplitude, and the DEMUX exhibited >180/spl deg/ phase margin from 4 to 50 Gb/s for 2/sup 31/-1 pseudorandom bit sequence (PRBS). Furthermore, 50-Gb/s back-to-back error-free operation for 2/sup 31/-1 PRBS was confirmed with the packaged MUX and DEMUX. 相似文献
5.
《Lightwave Technology, Journal of》2009,27(3):168-176
6.
《Photonics Technology Letters, IEEE》2009,21(16):1148-1150
7.
van den Borne D. Veljanovski V. Gaubatz U. Paquet C. Painchaud Y. Gottwald E. Khoe G.D. de Waardt H. 《Photonics Technology Letters, IEEE》2007,19(14):1069-1071
Phase ripple impairments induced through cascaded fiber Bragg gratings (FBGs) are discussed for 42.8-Gb/s transmission. We show the feasibility of transmission over 1140 km (12 times 95 km) using return-to-zero differential quadrature phase-shift keying modulation and FBG-only dispersion compensation. We further compare FBGs with dispersion-compensating fiber for dispersion compensation and analyze the influence of wavelength detuning. 相似文献
8.
《Photonics Technology Letters, IEEE》2009,21(11):745-747
9.
超高速模数转换器(ADC)是软件无线电、高速数据采集和宽带数字化雷达的关键组成部分.附带校准技术的折叠内插ADC具有等同快闪(FLASH)ADC的高转换速度,是设计超高速ADC的最佳选择,但仍需综合考虑各项指标来时行校准方法设计及芯片架构优化. 相似文献
10.
An 8-Gb/s 0.3-μm CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear phase-locked loop that achieves a loop bandwidth of 35 MHz, phase margin of 50°, and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8 Gb/s data are successfully detected by the receiver after a 10-m coaxial cable. The 2×2 mm2 chip consumes 1.1 W at 8 Gb/s with a 3-V supply 相似文献
11.
Takahashi H. Al Amin A. Jansen S. L. Morita I. Tanaka H. 《Lightwave Technology, Journal of》2010,28(4):406-414
12.
Transmission of 32-Tb/s Capacity Over 580 km Using RZ-Shaped PDM-8QAM Modulation Format and Cascaded Multimodulus Blind Equalization Algorithm 总被引:1,自引:0,他引:1
Zhou X. Yu J. Huang M.-F. Shao Y. Wang T. Magill P. Cvijetic M. Nelson L. Birk M. Zhang G. Ten S. Matthew H. B. Mishra S. K. 《Lightwave Technology, Journal of》2010,28(4):456-465
13.
High-Spectral-Efficiency 114-Gb/s Transmission Using PolMux-RZ-8PSK Modulation Format and Single-Ended Digital Coherent Detection Technique 总被引:1,自引:0,他引:1
《Lightwave Technology, Journal of》2009,27(3):146-152
14.
Festus Idowu Oluwajobi Dong-Nhat Nguyen 《International Journal of Electronics》2013,100(12):1919-1937
The paper examines the performance of Modified Manchester (MM) modulation scheme over wavelength division multiplexing (WDM) in high-speed optical communication links. The MM as a new modulation technique has a narrow spectral width compared to conventional Manchester coding, which allows its implementation in WDM systems beneficial. In this study, the performance characteristics of MM and conventional Manchester modulation formats are assessed in WDM system at 10 Gb/s bitrate for each channel, for the least allowable channel spacing as well as tolerance to chromatic dispersion (CD). It is revealed from the results of simulation that MM performs meaningfully well in comparison with conventional Manchester in terms of tolerance against narrow optical filtering, spectral efficiency, which is improved by 32% and CD tolerance, which is improved by +100 ps/nm. Sixteen wavelength channels (16 × 10 Gb/s) are modulated to provide 160 Gb/s data capacity, which was transmitted successfully over 224 km standard single mode fibre (SSMF) using MM while the conventional Manchester only covered about 157 km. 相似文献
15.
Coherent Optical 25.8-Gb/s OFDM Transmission Over 4160-km SSMF 总被引:1,自引:0,他引:1
Jansen S.L. Morita I. Schenk T.C.W. Takeda N. Tanaka H. 《Lightwave Technology, Journal of》2008,26(1):6-15
We discuss coherent optical orthogonal frequency division multiplexing (CO-OFDM) as a suitable modulation technique for long-haul transmission systems. Several design and implementation aspects of a CO-OFDM system are reviewed, but we especially focus on phase noise compensation. As conventional CO-OFDM transmission systems are very sensitive to laser phase noise a novel method to compensate for phase noise is introduced. With the help of this phase noise compensation method we show continuously detectable OFDM transmission at 25.8 Gb/s data rate (20 Gb/s after coding) over 4160-km SSMF without dispersion compensation. 相似文献
16.
Seong-Jun Song Sung Min Park Hoi-Jun Yoo 《Solid-State Circuits, IEEE Journal of》2003,38(7):1213-1219
A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply. 相似文献
17.
《Photonics Technology Letters, IEEE》2009,21(22):1680-1682
18.
An 8-b flash analog-digital (A/D) converter (ADC) LSI for high-speed data acquisition systems such as digital oscilloscopes and wave digitizers is described. This converter can convert analog input signals over the Nyquist frequency (up to 200 MHz) at a conversion rate of 300 megasamples per second (Ms/s) without glitch errors. In addition, it can be operated at up to 440 Ms/s when input frequency is as low as 100 kHz. This ADC is fabricated by a 2.5-μm, 10-GHz f T , Si bipolar technology called the advanced sidewall base contact structure (advanced SICOS) technology. For high-performance glitch error suppression, an inhibitory circuit and a comparator design with an inner clock buffer are developed. Both techniques require few hardware additions 相似文献
19.
《Lightwave Technology, Journal of》2009,27(4):396-408
20.
A 1024-b, rate-1/2, soft decision low-density parity-check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The decoder features a parallel architecture that supports a maximum throughput of 1 Gb/s while performing 64 decoder iterations. The parallel architecture enables rapid convergence in the decoding algorithm to be translated into low decoder switching activity resulting in a power dissipation of only 690 mW from a 1.5-V supply 相似文献