应用于Bluetooth频率合成器的可编程分频器设计

设计了一种应用于Bluetooth整数频率合成器的可编程分频器.电路设计采用SMIC 0.18 μm CMOS工艺和Cadence Spectre仿真器.整个分频电路由基于SCL(Source-Coupled Logic)结构实现的16/17双模预分频电路和基于标准数字逻辑单元实现的可编程计数器组成.频率合成器的信道间隔设为1 MHz.通过对可编程计数器进行预置数,分频器覆盖整个ISM信号频段(2400～2478 MHz).     

基于90 nm CMOS工艺的37 GHz分频器

对高速分频器的注入锁定特性进行了研究,并实现了一个基于电流模逻辑的分频器。该分频器采用了电感峰值技术,分频范围可达25~37.3 GHz,电源电压为1.2 V,功耗为24 mW。芯片采用TSMC 90 nm CMOS工艺设计制造,并给出了测试结果。     

0.18μm CMOS PLL频率综合器中可编程分频器的设计与实现

介绍了用于WLAN802．11a收发信机的PLL频率综合器中可编程分频器的设计。基于ARTISAN标准单元库对可编程分濒器进行了设计，详细介绍了自定义线负载模型、版图规划、时钟树综合、布局布线、静态时序分析等VlSI设计流程．并通过前端和后端设计的相互协作对电路进行了反复优化。最后给出了可编程分频器的后仿真结果、芯片照片和测试结果，芯片内核面积1360．5μm^2，测试结果表明设计符合要求。     

5G8630输出频率可编程分频器的原理与应用

5G8630输出频率可编程分频器是上海元件五厂自行设计制造的新型可编程分频器件，它具有功耗低、输入阻抗高、集成性强、使用灵活方便等特点。文中介绍了5G8630的主要参数和引脚功能，并给出了两种分频电路的连接图及分频电路波形。     

可扩展分频比范围的射频可编程分频器设计

介绍了一种可扩展分频比范围的射频可编程分频器,该电路包括输入放大器、前置2分频电路、4级除2/除3分频单元和15位可编程计数器。该分频器应用于频率合成器中,采用0.35μm BiCMOS工艺实现,电源电压3.3V,电源电流80mA。射频输入12GHz时灵敏度-10~10dBm。分频比从16到219-1可调。     

应用于频率合成器的宽分频比CMOS可编程分频器设计

提出一种应用于射频频率合成器的宽分频比可编程分频器设计。该分频器采用脉冲吞吐结构,可编程计数器和吞脉冲计数器都采用改进的CMOS源极耦合（SCL）逻辑结构的模拟电路实现,相对于采用数字电路实现降低了电路的噪声和减少了版图面积。同时,对可编程分频器中的检测和置数逻辑做了改进,提高分频器的工作频率及稳定性。最后,采用TSMC的0.13μm CMOS工艺,利用Cadence Spectre工具进行仿真,在4.5 GHz频率下,该分频器可实现200515的分频比,整个功耗不超过19 mW,版图面积为106μm×187μm。     

一种可编程的2.4GHz CMOS多模分频器

采用0.35μm CMOS工艺设计并实现了一种多模分频器.该多模分频器由一个除4或5的预分频器和一个除128～255多模分频器在同一芯片上连接而成;在电路设计中,分析了预分频器功耗和速度之间的折中关系,根据每级单元电路的输入频率不同对128～255多模分频器采用了功耗优化技术;对整个芯片的输入输出PAD进行了ESD保护设计;该分频器在单端信号输入情况下可以工作到2.4GHz,在差分信号输入下可以工作到2.6GHz以上;在3.3V电源电压下,双模预分频器的工作电流为11mA,多模分频器的工作电流为17mA;不包括PAD的芯片核心区域面积为0.65mm×0.3mm.该可编程多模分频器可以用于2.4GHz ISM频段锁相环式频率综合器.     

一种0.18 μm CMOS可编程分频器的设计

采用标准0.18 μm CMOS工艺,设计了一种可编程分频器。基于基本分频单元的特殊结构,对除2/除3单元级联式可编程分频器的关键模块进行改进,将普通的CML型锁存器集成为包含与门的锁存器,提高了电路的集成度,有效地降低了电路功耗,提升了整体电路速度,并使版图更为紧凑。后仿真结果表明,在1.8 V电源电压,输入频率f_in=1 GHz的情况下,可实现任意数且步长为1的分频比,相位噪声为-173.1 dBc/Hz @ 1 MHz,电路功耗仅为9 mW。     

一种多模可编程前置分频器的设计

针对目前大多数射频可调谐芯片中前置分频器多为双模结构,设计了一种基于2/3分频单元的可编程多模(64～127)前置分频器.采用0.35 μm SiGe BiCMOS工艺,在工作电源电压Vdd=5 V,输入频率为2.2 GHz的情况下,可实现分频比为64～127之间的可编程多值分频,功耗为37.18 mW.     

数模混合GHz级频率综合器下变频模块设计

介绍了一种应用于GHz级高速频率合成器的数模混合下变频模块.采用了高速射频双模预分频器与数字逻辑综合生成的可编程吞脉冲分频器相结合的设计方法.双模预分频实现了高速低抖动低功耗,双模预分频器工作在除8状态输出133MHz频率时,均方差抖动小于2ps;可编程吞脉冲分频器算法灵活、设计复用性强,该算法可以灵活运用到许多复杂频率综合系统.相比较而言,该设计获得了更好的高频电路性能与设计复用性.     

83GHz InP DHBT静态分频器

A static frequency divider is presented using 0.7μm lnP DHBTs with 280 GHz ft/fmax. The divider is based on ECL master-slave D-flip-flop topology with 30 HBTs and 20 resistors with a chip size 0.62 ×0.65 mm^2. The circuits use peaking inductance as a part of the loads to maximize the highest clock rate. Momentum simulation is used to accurately characterize the effect of the clock feedback lines at the W band. Test results show that the divider can operate from 1 GHz up to 83 GHz. Its phase noise is 139 dBc/Hz with 100 kHz offset. The power dissipation of divider core is 350 mW.     

Ka波段具有宽锁定范围高注入灵敏度的分频器*

This paper proposes a direct injection-locked frequency divider（ILFD） with a wide locking range in the Ka-band. A complementary cross-coupled architecture is used to enhance the overdriving voltage of the switch transistor so that the divider locking range is extended efficiently. New insights into the locking range and output power are proposed. A new method to analyze and optimize the injection sensitivity is presented and a layout technique to reduce the parasitics of the cross-coupled transistors is applied to decrease the frequency shift and the locking range degradation. The circuit is designed in a standard 90-nm CMOS process. The total locking range of the ILFD is 43.8% at 34.5 GHz with an incident power of –3.5 dBm. The divider IC consumes 3.6 mW of power at the supply voltage of 1.2 V. The chip area including the pads is 0.50.5 mm2.     

Wide division ratio range programmable frequency divider with close-to-50% output duty-cycle

A novel wide division ratio (DR) range programmable frequency divider is presented in this article, which is based on the proposed divide-by-2/3/4 cell. The divider's output is buffered by a divide-by-2 cell; hence, it can achieve the close-to-50% output duty-cycle. The DRs can be set via the convenient provisions of binary bits. When the DR is even, the output duty-cycle is exactly 50%. If the DR is odd, the output duty-cycle is k/(2?k?+?1), where k is a natural number, therefore, it becomes close-to-50% with an increasing k. A divider with eight DR control bits, which can realise the DRs from 8 to 511, is implemented in standard 0.18?µm complementary metal-oxide semiconductor technology, the die area is 0.02?mm². The measured results show that the divider can obtain 44.4–50% output duty-cycle which corroborates with the calculation.     

An InGaAs/InP 40 GHz CML static frequency divider

Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology’s ability to implement high speed digital and integrated high performance mixed-signal circuits.We report a 2:1 static frequency divider in InGaAs/InP heterojunction bipolar transistor technology.This is the first InP based digital integrated circuit ever reported on the mainland of China. The divider is implemented in differential current mode logic(CML) with 30 transistors.The circuit operated at a peak clock frequency of 40 GHz and dissipated 650 mW from a single -5 V supply.     

40GHz InGaAs/InP CML 结构静态分频器

Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology's ability to implement high speed digital and integrated high performance mixed-signal circuits.We report a 2:1 static frequency divider in InGaAs/InP heterojunction bipolar transistor technology.This is the first InP based digital integrated circuit ever reported on the mainland of China. The divider is implemented in differential current mode logic(CML) with ...     

Low-power wide-locking-range injection-locked frequency divider for OFDM UWB systems

This paper describes a divide-by-two injection-locked frequency divider (ILFD) for frequency synthesizers as used in multiband orthogonal frequency division multiplexing (OFDM) ultra-wideband (UWB) systems. By means of dual-injection technique and other conventional tuning techniques, such as DCCA and varactor tuning, the divider demonstrates a wide locking range while consuming much less power. The chip was fabricated in the Jazz 0.18 μm RF CMOS process. The measurement results show that the divider achieves a locking range of 4.85 GHz (6.23 to 11.08 GHz) at an input power of 8 dBm. The core circuit without the test buffer consumes only 3.7 mA from a 1.8 V power supply and has a die area of 0.38 × 0.28 mm2. The wide locking range combined with low power consumption makes the ILFD suitable for its application in UWB systems.     

适用于OFDM UWB 系统的低功耗，大锁定范围注入锁定分频器

This paper describes a divide-by-two injection-locked frequency divider （ILFD） for frequency synthesizers as used in multiband orthogonal frequency division multiplexing （OFDM） ultra-wideband （UWB） systems. By means of dual-injection technique and other conventional tuning techniques, such as DCCA and varactor tuning, the divider demonstrates a wide locking range while consuming much less power. The chip was fabricated in the Jazz 0.18μm RF CMOS process. The measurement results show that the divider achieves a locking range of 4.85 GHz （6.23 to 11.08 GHz） at an input power of 8 dBm. The core circuit without the test buffer consumes only 3.7 mA from a 1.8 V power supply and has a die area of 0.38×0.28 mm^2. The wide locking range combined with low power consumption makes the ILFD suitable for its application in UWB systems.     

7-27GHz 动态源极耦合逻辑二分频器

本文介绍了一款高速宽带二分频器的设计与分析。设计采用动态源极耦合逻辑结构,由两级动态负载主从D触发器构成,工作频率高,功耗低。这款分频器工作范围为7~27GHz,在1.2V工作电压下最低功耗仅为1.22mW。整个频带内输入灵敏度仅为25.4dBm。设计采用90nm CMOS工艺,使用了两个片上螺旋电感,芯片面积为685um*430um。     

10～37GHzCMoS四分频器的设计

给出基于0．13μmCMOS工艺、采用单时钟动态负载锁存器设计的四分频器。该四分频器由两级二分频器级联而成。级间采用缓冲电路实现隔离和电平匹配。后仿真结果表明其最高工作频率达37GHz,分频范围为27GHz。当电源电压为1．2V、工作频率为37GHz时,其功耗小于30mW,芯片面积为0．33-0．28mm2。     

A fractional-N frequency synthesizer for WCDMA/Bluetooth/ZigBee applications

esented.