Collector recombination lifetime from the quasi-saturation analysisof high-voltage bipolar transistors

A novel method of measuring the collector recombination lifetime, which is independent of emitter effects, is presented by extending the quasi-saturation analysis of high-voltage bipolar transistors to the high-current-density regime. The technique is supported by theory, and experimental results are presented on transistors fabricated with different emitter properties. This is a nondestructive method and gives the lifetime values at the current densities normally encountered when the transistor is in actual operation. The values for the collector recombination lifetime obtained by the present method are independent of the properties of the emitter region     

A unified circuit model for bipolar transistors including quasi-saturation effects

This paper describes a compact model for bipolar transistors which includes quasi-saturation effects. The assumptions used in the formulation of this model are clearly stated and justified, and a step by step derivation of the model equations is presented. These equations model both de and charge storage effects. Parameter extraction techniques are qualitatively described and the compact model is evaluated using detailed physical simulations of a high voltage bipolar transistor. In addition, simulations employing this model are compared with measurements and are found to be in excellent agreement.     

Circuit modeling of collector current spreading effects in quasi-saturation for advanced bipolar transistors

The advanced bipolar transistor operating in the quasi-saturation region has been modeled, including collector current spreading effects. It is shown that the multidimensional collector current spreading, resulting from high carrier concentration gradient in the collector, ameliorates quasi-saturation effects in the d.c. and transient operation. The mechanism of collector spreading is investigated by physical device simulations. SPICE circuit simulations employing the collector spreading model are compared with measurements and are found to be in excellent agreement.     

Study of the quasi-saturation effect in VDMOS transistors

The quasi-saturation effect in VDMOS transistors is studied in detail. It is shown that such behavior is due to carrier velocity saturation in the JFET region of the device. Two-dimensional numerical simulation is carried out to study the quasi-saturation effect and its relation to different device design parameters. Experimental results over a wide range of voltage and current levels are used to verify calculated dc characteristics. In addition, the design constraint on p-body spacing in order to avoid the quasi-saturation effect is defined.     

Measurement of the base resistance of bipolar transistors

By measuring the transistor parameters hfe and yfb as functions of frequency, it is possible to determine the base resistance of bipolar transistors. This method has proved to be fast and accurate over a relatively large current range for integrated-circuit transistors, as well as for many types of discrete transistors.     

Measurement of series collector resistance in bipolar transistors

A new method has been devised to measure directly the series collector resistance (r/SUB c/) of monolithic bipolar n-p-n transistors. The method uses the parasitic substrate p-n-p and the reverse n-p-n associated with each integrated n-p-n transistor to detect the internal collector-base voltage. The effects of temperature, conductivity modulation, and mobility on the collector resistance can be measured directly. Measurements on a range of devices indicate standard techniques such as the forced beta method measure only a fraction of the total collector resistance. The present technique yields results in good agreement with theoretically calculated values of r/SUB c/. This method is amenable to automated measurement systems.     

Modelling of VHF and microwave power transistors operating in quasi-saturation

The modelling of VHF and microwave power transistors operating under quasi-saturation conditions is treated. Physical effects in the collector region are considered to be dominant in these devices under such circumstances, and a representation of the collector involving a variable-width charge-storage region, modelled in two-lump form, is developed in order to characterize device behaviour. A systematic procedure is presented for the evaluation of the parameters of the collector region model. The model has demonstrated its ability to describe device characteristics and performance under d.c., step transient and large signal sinusoidal drive conditions; typical results are presented.     

Measurement of the low-current base and emitter resistances of bipolar transistors

A new ac method is proposed to measure the emitter and base resistances of bipolar transistorsat low current levels at which the effective transistor geometry is given by the processing and is unaffected by the changes induced by high currents. The technique is based on a measurement of the input impedance at frequencies below about 50 MHz. It is particularly suited for the measurement of the physical emitter resistance of scaled transistors. The method is illustrated on microwave transistors with metal contacts and on self-aligned digital transistors with polysilicon contacts. A comparison of the results obtained using this method with those from dc methods operating at high currents can be used to explore the current dependencies of the resistances. The technique is applicable both for homojunction and heterojunction transistors.     

Saturation in bipolar transistors

A computer solution is obtained for the voltage drop across a saturated transistor as a function of IC/IB, on the assumption that the emitter and collector currents may each be expressed as a superposition of three voltage-dependent terms. The result, showing good agreement with experiment, is a family of curves with the base current as the variable parameter.     

Herb's bipolar transistors

The profound influence of Herbert Kroemer's ideas on the development of high-performance bipolar transistors is described. The historical context and subsequent development of innovations such as the drift base, achieved through concentration gradients and later with semiconductor bandgap grading, the use of wide bandgap emitters, concepts of collector-up transistors, and the introduction of new heterojunction materials, are reviewed     

Silicon-on-insulator bipolar transistors

Thin-film lateral n-p-n bipolar transistors (BJT) have been fabricated in moving melt zone recrystallized silicon on a 0.5-µm silicon dioxide substrate thermally grown on bulk silicon. Current-voltage characteristics of devices with different base widths (5 and 10 µm) have been analyzed. The use of a metal gate over oxide covering the base region has allowed the devices to be operated as n-channel MOSFET's as well thus surface effects on device characteristics have been investigated under varying gate-bias voltages. Maximum dc current gain values of 2.5 were achieved with a 5-µm base width and values around 0.5 with a 10-µm base width. Higher gain values were impeded by onset of high-level injection which occurred at low currents because of light base doping of these devices.     

Measurement of the electron ionization coefficient at low electricfields in GaAs-based heterojunction bipolar transistors

Values of the electron ionization coefficient α_n in 〈100〉 GaAs extending the previously available data by two orders of magnitude, down to 1 cm^-1, are presented. The data are directly extracted from the multiplication factor, M-1, measured in lightly doped collector n-p-n AlGaAs/GaAs heterojunction bipolar transistors (HBT's). It is shown that the sensitivity of the technique is limited by the early effect, whose influence can be reduced by driving the device at constant emitter-base bias and by using heavily doped base regions. HBT's can provide simultaneously high base doping and current gain, and represent therefore an excellent tool for these measurements     

Concise transient SPICE model for bipolar power transistor quasi-saturation simulation

A concise transient SPICE model is presented in this paper to predict both the static and the switching behaviour of power transistors, with emphasis placed on quasi-saturation effects. The model is proposed to simulate both ohmic and non-ohmic quasi-saturation phenomena by automatically adjusting the hole injection ratio term. The model incorporates the currently used Gummel-Poon (GP) model and an additional charge-control relation for the transistor's epitaxial collector. The turn-off charge removal phenomenon is not modelled specifically; however, the charge-control equation for the epitaxial collector region may partly simulate this effect where the quasi-saturation region is entered. The validity of the model is verified by comparison between the original SPICE bipolar junction transistor model and experimental data for both DC and turn-on conditions. Methods for determining the model parameters are described.     

Intermodulation in heterojunction bipolar transistors

The modeling of small-signal intermodulation distortion (IMD) in heterojunction bipolar transistors (HBTs) is examined. The authors show that IMD current generated in the exponential junction is partially canceled by IMD current generated in the junction capacitance, and that this phenomenon is largely responsible for the unusually good IMD performance of these devices. Thus, a nonlinear model of the HBT must characterize both nonlinearities accurately. Finally, the authors propose a nonlinear HBT model suitable for IDM calculations, show how to measure its parameters, and verify its accuracy experimentally     

Measurement method for accurate extraction of the base-to-emitterintrinsic and peripheral capacitances of bipolar transistors

A simple measurement method to determine the intrinsic and peripheral emitter junction capacitances is described. The method is based on measurements of BJT's with different emitter geometries and is demonstrated on transistors of an advanced BiCMOS technology. The method can be applied directly to standard deep-submicrometer devices. No special test devices are required. By determining peripheral capacitance for different processes, the method enables the examination of process schemes designed to suppress the effect of the peripheral emitter on the transistor action. The method also provides a useful approach to monitor the scaling behavior of the intrinsic and peripheral capacitances. Results indicate the peripheral capacitance starts dominating the total capacitance as the emitter is scaled into the submicrometer range. For devices with quarter micron emitter widths, the peripheral capacitance is found to be 3 to 4 times higher than the intrinsic capacitance, and puts a fundamental limitation on device design     

Fully ion-implanted bipolar transistors

Technology for the fabrication of fully ion-implanted bipolar transistors with arsenic emitters and boron bases is described. This technology results in extremely uniform distributions of electrical parameters, e.g,, hFE= 113 with a standard deviation of 1.3 across a wafer. In addition, it can produce a wide range of doping profiles and hence, a wide range of device performance. Using very similar processing schedules, transistors with hFEfrom 20 to >5000 and with fT's from 1.5 to 8.1 GHz have been made. The features of implanted arsenic which make it an excellent emitter are: 1) it can be implanted to high doses with only a small deep side tail which has a negligible effect on the typical transistor base; 2) because of the concentration dependence of its diffusion constant, it forms a very abrupt profile after diffusion; and 3) when diffused a short distance (∼1000 Å) away from the implanted region, high-lifetime material can be incorporated into the emitter and hence, high-gain low-leakage transistors can be made. When the arsenic emitter is combined with a double-peaked boron-implanted base, precise independent control of the active and inactive base properties of the device can be achieved. This independence allows considerable latitude in the choice of device parameters for fully implanted bipolar transistors.     

Degradation of gain in bipolar transistors

In this paper hot carrier related aging of n-p-n bipolar transistors is investigated experimentally and theoretically in order to bring physical insight into the bipolar h_FE (common emitter current gain) degradation. Electrical stress experiments are performed on transistors with different base doping profiles at varying temperatures. Detailed process simulations are performed to determine the doping profiles of the base-emitter junction. Monte Carlo transport simulations are then performed at different temperatures and bias conditions to determine the electron and hole distribution functions in the base-emitter junction. AT&T's 0.8 μm BICMOS technology is used to fabricate the experimental bipolar structures. For this non-self aligned technology we attribute h_FE degradation to the presence of hot holes and secondary electrons which are generated by hot hole impact ionization. This feedback due to impact ionization has a dominant effect on the high energy tails of the distribution of both holes and electrons even when the overall current multiplication is low. Simple hot electron energy transport models do not contain the complexity to properly describe ionization feedback and carrier heating, and are therefore inadequate. An exponential dependence of the transistor lifetime on BV_EBO is deduced for constant voltage stress (V_stressEBO) conditions, confirming the importance of secondaries in the process of degradation