MNOS memory transistors in simple memory arrays

The basic properties of MNOS memory transistors as digital memory elements are reviewed. Optimization procedures for obtaining maximum memory retention are presented and possible arrangements of memory transistors in simple arrays and writing and reading procedures for such arrays are discussed.     

Nonvolatile analog memory in MNOS capacitors

Long-term storage of analog signals of wide dynamic range has been successfully demonstrated for the first time in single MNOS capacitors. After a reset state is established by majority carrier tunneling, measured pulses of light are used to generate minority carriers which tunnel to nitride traps and in turn induce shifts in the flat-band voltage proportional to the minority carrier charge. Linear voltage windows of 12 volts are observed, and logarithmic decay rates are as low as 30 mV per decade of storage time per volt of initial flat-band shift. Analog signals can be stored linearly over a dynamic range of 40 dB for 30 hours.     

Rotating MNOS disk memory device

This paper presents a new recording and reproducing system using a disk-type charging medium, i.e., a rotating MNOS disk memory device, which consists of a single stationary 'metal' electrode and an 'NOS' disk rotating in contact with it. This is capable of reading information immediately after writing it, and also capable of easily rewriting part or all of the written information without aid of any physical or chemical processing, by overlay-recording new information over the old, as well as permitting the recording of information at a very high density. This type of electrically erasable memory has the potential for storing a bit of information in an area of less than 1 µm². Using a prototype disk made of a 3-in-diameter silicon wafer, we recently demonstrated a single-field TV memory.     

Theory of MNOS memory transistor

A theory on the switching behavior of the metal-Si3N4-SiO2-semiconductor (MNOS) memory transistor is presented which is consistent with the experimentally observed facts. The theory treats the switching process as being initially predominantly direct band-to-band tunneling and then dominated by modified-Fowler-Nordheim tunneling. The large-signal mathematical treatment includes both of these tunneling terms. The resultant charge-transport equation is rather complex; a numerical method is needed to obtain an exact solution, However, a grossly approximate closed-form solution has been obtained, which indicates that the transferred charge is initially a linear function of time and then logarithmic. This is similar to many of the previous theories. However, the coefficients in the current and charge solutions of the present theory contain the essential material, device, and operating parameters which are absent in previous theories. This makes the present model readily usable as a guide in the design and optimization of MNOS devices.     

The light-sensitive MNOS memory transistor

In a simple memory application the threshold voltage VTof an MNOS transistor is switched by means of write and erase pulses of opposite polarities between two levels, representing logical ONEs and ZEROs. It is shown that by isolating the source and drain during the write pulse, the magnitude of the VTshift can be made dependent on the intensity of light on the MNOS device. By choosing the light intensity and the width of the write pulse properly, the device can be made to operate in either a digital or analog mode. The theory of this effect, applicable to both transistors and capacitors, is developed by generalizing the well-understood behavior of the MNOS memory device to include conduction in the silicon space-charge region. The operation of the device depends on the current-field relationships for the nitride, oxide, and silicon space-charge layers. It is shown how these three functions may be obtained from steady-state I-V measurements on the MNOS device. Good agreement is found between experimental and calculated charging curves for both transistors and capacitors.     

Writing of gold-doped MNOS memory devices

Gold diffusions at 900°C were carded out for diffusion times of 10, 20, and 40 min, on the MNOS devices with chemically oxidized n-type substrates. It was found that the switching speed with negative write pulses was improved 15-40 times over the control devices by 20-min gold diffusion. The writing speed is degraded with longer diffusion time because the increased accumulation of gold at the Si-SiO2interface serves effectively to increase the minority carrier relaxation time and scattering effects. It was also found that the presence of the acceptor traps and accumulation near and at the Si-SiO2interface in the MNOS system degrade the writing speed for positive pulses.     

MNOS/CCD nonvolatile analog memory

MNOS storage sites have been integrated with an n-channel CCD to produce a nonvolatile memory capable of storing sampled analog signals. Analog signals, sampled at the CCD input, are stored as trapped charge in the MNOS dielectric and may be replicated nondestructively after four days of storage with a linear dynamic range of 33 dB.     

Characteristics of interface-doped MNOS memory devices

The results of an investigation of the characteristics of MNOS memory devices are given in which the interface between the oxide and nitride was doped with a few monolayers of various refractory metals. In particular, write speeds of the order of microseconds could be obtained along with retention times which could be extrapolated to many decades. No temperature dependence could be found for the decay of stored charge between 77 K and 300°C, indicating that retention is normally dominated by Fowler-Nordheim back tunneling from the interface. Long time exposure to high gate voltages and write/erase cycling in excess of 1000 cycles sharply reduces the achievable memory window, and is accompanied by the copious generation of fast surface states, at least in p-channel devices.     

Characterization of thin-oxide MNOS memory transistors

A direct tunneling theory is formulated and applied to high-speed thin-oxide complementary metal-nitride-oxide-silicon (MNOS) memory transistors. Charge transport in the erase/write mode of operation is interpreted in terms of the device threshold voltage shift. The threshold voltage shift in the erase/write mode is related to the amplitude and time duration of the applied gate voltage over the full range of switching times. MNOS memory devices (X_{o}=25 Aring, X_{N} = 335 Aring) exhibit aDelta V_{th} = plusmn3V for an erase/writet_{p} = 100ns, which corresponds to an initial oxide field strengthE_{ox}= 1.2 times 10^{7}V/cm. The direct tunneling theory is applied to the charge retention or memory mode in which charge is transported to and from the Si-SiO2interface states. The rate of charge loss to interface states is influenced by electrical stress which alters the interface state characteristics. We discuss the fabrication of complementary high-speed MNOS memory transistors and the experimental test procedures to measure charge transport and storage in these devices.     

Recent progress in bipolar transistor technology

Recent developments in high speed silicon bipolar device technologies are reviewed. Bipolar device structures that include polysilicon are key technologies for improving circuit characteristics. Double polysilicon bipolar device structures, in particular, have made it possible both to form shallow junctions and to reduce device dimensions. Recent progress of silicon bipolar transistor technology using SiGe and the use of the SOI technology to obtain high speed operations are also reviewed     

Electrically erasable nonvolatile optical MNOS memory device

A new type of nonvolatile optical memory device composed of a MNOS FET with a photosensitive region is proposed. Based upon charge transport induced by voltage change across a double insulator layer under illumination, the present device can be operated in a broad wavelength spectrum from the infrared to the visible region when provided with a d.c. bias voltage. It is found that the charge transport is a function of the exposure time as well as of the intensity of the incident light. An operation mechanism is proposed based upon the experimental results.     

A content-addressable memory cell with MNOS transistors

Describes a new associative memory cell in which MNOS transistors are used as storage elements. The memory can perform functions as a read-only memory and at the same time as a read-write memory. The cell can be read as a random-access memory or as a content-addressable memory. As a CAM certain bits can be masked out, i.e., not compared with the stored bits. The comparison can also be controlled from the memory by the stored words. Since the word length or combinations of normal words can be stored in one word of the memory, fewer memory cells are needed than in an ordinary memory. Searches for groups of words (prime implicands) can be performed. Memory cells with an area of 5000-m- have been built to demonstrate the feasibility of the MNOS-CAM.     

Nonvolatile CCD memory with MNOS storage capacitors

The volatility of information stored in a charge-coupled device can be avoided by storing the information in metal-nitride-oxide-silicon capacitors added to a CCD. In the following, the function, layout, and measured results of test circuits are described, and different layouts of such memory circuits are discussed.     

Test results on an MNOS memory array

The NCR 2050 MNOS memory chip, developed under Air Force contract for frequency-preset applications in communications equipment, has been tested and evaluated. Results on retentivity, writing characteristics, pattern sensitivity, and endurance are presented.     

Endurance of thin-oxide nonvolatile MNOS memory transistors

A discussion of the factors which determine the endurance of thin-oxide MNOS memory transistors is presented. Si-SiO2interface states are influential in the early stages of erase/write cycling, while charge movement into the nitride controls the long term cycling characteristics. Other important variables include the method of preparation of the thin-oxide region, its composition, dielectric properties and thickness; the high density of spatially localized traps near the nitride-oxide interface; the low conductivity Si3N4dielectric, and electric field strengths. Optimizing these variables permits MNOS memory transistors to be operated with high endurance, reliably to beyond 10¹⁰erase/write cycles with ±20-V, 100-µs pulses and demonstrate a minimum 2-V memory window at 2900 h retention time.     

Charge distribution in the nitride of MNOS memory devices

The steady state charge distribution for weakly occupied traps is a universal function of position over most of the nitride, with dielectric constant and Frenkel-Poole coefficient α being the only material parameters. The transient charge distribution for constant current pulses is approximated by truncating the steady state distribution and the resulting relation between charge content and its centroid is used to fit experimental data which provides α-values of a reasonable magnitude. A diffusive component of charge motion during application of alternating polarity voltage pulses is identified, and its diffusion coefficient is related to the Frenkel-Poole emission rate from traps.     

Trapping,emission and generation in MNOS memory devices

This study is concerned with trapping phenomena occuring at the semiconductor-oxide interface and in the nitride layer of variable-threshold metal-nitride-oxide-semiconductor (MNOS) memory devices. The technique consits of biasing the device in such a manner as to charge or discharge either the interface traps or the nitride traps, or both sets of traps simultaneously. The device is then cooled to low temperature with the bias still applied, and at the low temperature the biasing condition is changed, in order to induce the device into a non-steady mode that is quasi-stable at the low temperature. The temperature of the device is then raised at a constant rate, and the resulting current vs temperature (I-T) characteristics is found to be rich in structure. By means of a series of systematic experiments the various portions of the I-T characteristic are identified with emission of electrons from interface states and the nitride traps, and surface generation. From this data the energy distribution of interface states is determied. It is shown that the memory charge in the nitride is distributed throughout the nitride, and temporary memory charge and semi-permanent memory charge are distinguished.     

New scaling guidelines for MNOS nonvolatile memory devices

New phenomena in MNOS retention characteristics that originate from stored charge distribution are described and new scaling guidelines are indicated. The most significant phenomenon is that write-state retentivity is less dependent on the programmed depth, and is improved by reducing silicon nitride thickness. This behavior suggests that write-state charges are distributed rectangularly, while erase-state charges are distributed exponentially. The lower limit of the programming voltage is determined by write-state retentivity and not erase-state retentivity, and the write-state charge distribution depth determines the lower limit of silicon nitride thickness. The upper limit of the programming voltage is determined by erase-state retentivity after erase/write cycles. The scaling guidelines indicate that 16-Mb EEPROMs can be designed using MNOS memory devices     

A new MNOS memory element—the tunnel diode

MNOS (Metal-Nitride-Oxide-Silicon) memory devices commercially available today consist of transistor arrays where each device represents a memory bit. Typical devices have densities greater than 8 K bits and are generally manufactured on epitaxial based processes for isolation. The state of each bit is determined by its threshold voltage and is sensed by interpreting if the transistor is in the “off” or “on” condition. A new MNOS memory element is described where detection of junction tunnelling current is used as the sense mechanism. Substrate forms the “third” terminal and the element has the possibility of being the basis of a dense array. The technique can be developed in p or n channel and can be used as an add-on to volatile random access memories.