Fabrication of high-speed InP/InGaAs/InP DHBT with a new self-aligned metallization technique for reduced base resistance

A new self-aligned emitter–base metallization (SAEBM) technique with wet etch is developed for high-speed heterojunction bipolar transistors (HBTs) by reducing extrinsic base resistance. After mesa etch of the base layer using a photo-resist mask, the base and emitter metals are evaporated simultaneously to reduce the emitter–base gap (S_EB) and base gap resistance (R_GAP). The InP/InGaAs/InP double heterojunction bipolar transistor (DHBT) fabricated using the technique has a reduced R_GAP, from 16.48 Ω to 4.62 Ω comparing with the DHBT fabricated by conventional self-aligned base metallization (SABM) process. Furthermore, we adopt a novel collector undercut technique using selective etching nature of InP and InGaAs to reduce collector–base capacitance (C_CB). Due to the reduced R_GAP, the maximum oscillation frequency (f_max) for a 0.5 μm-emitter HBT is improved from 205 GHz to 295 GHz, while the cutoff frequency (f_T) is maintained at around 300 GHz.     

The performance of resonant tunnelling transistors

An investigation is reported of the performance of the resonant tunnelling transistor based on the solution of Schrödinger's equation. The calculated J-V (current density-voltage) characteristics have been obtained and from the equivalent circuit, which is derived from these calculations, the cut-off frequency f_T and the maximum frequency of oscillation f_max have been estimated.     

A low-cost horizontal current bipolar transistor (HCBT) technology for the BiCMOS integration with FinFETs

A novel Horizontal Current Bipolar Transistor (HCBT) is processed with the scaled down dimensions and the improved technology. The active transistor region is built in the defect-free sidewall of the 580 nm wide n-hills in the (1 1 0) wafer, implying the reduction of the parasitic region's volume, i.e. the extrinsic base and the collector. The fabricated HCBT exhibits the cutoff frequency (f_T) of 21.4 GHz, the maximum frequency of oscillations (f_max) of 32.6 GHz and the collector–emitter breakdown voltage (BV_CEO) of 5.6 V, which are the highest f_T and the highest f_TBV_CEO product among the lateral bipolar transistors (LBTs).     

异质结双极晶体管高频噪声建模及分析

提出了一个T等效异质结双极晶体管高频噪声电路模型.该模型是对通常用在硅双极晶体管中的Hawkins噪声模型进行改进得到的,主要的改进包括发射极理想因子、发射极电阻、内部BC结电容、外部BC结电容和其它寄生元素对器件噪声性能的影响.为了从等效噪声电路模型中计算出精确的噪声参数,采用了噪声相关矩阵法来计算噪声参数,从而避免了在等效电路变换中可能产生的简化和复杂的噪声测量.进一步利用该模型分析了等效电路元素对器件最小噪声系数的影响,分析计算结果和物理解释一致.同时通过基于异质结双极晶体管器件物理的公式,给出了器件参数对器件最小噪声系数的影响.     

A new two-dimensional C-V model for prediction of maximum frequency of oscillation (fmax) of deep submicron AlGaN/GaN HEMT for microwave and millimeter wave applications

An analytical two-dimensional capacitance-voltage model for AlGaN/GaN high electron mobility transistor (HEMTs) is developed, which is valid from a linear to saturation region. The gate source and gate drain capacitances are calculated for 120 nm gate length including the effects of fringing field capacitances. We obtain a cut-off frequency (f_T) of 120 GHz and maximum frequency of oscillations (f_max) of 160 GHz. The model is very useful for microwave circuit design and analysis. Additionally, these devices allow a high operating voltage V_DS, which is demonstrated in the present analysis. These results show an excellent agreement when compared with the experimental data.     

DC parameter extraction of equivalent circuit model in InGaAsSb heterojunction bipolar transistors including non-ideal effects in the base region

This paper presents the DC parameter extraction of the equivalent circuit model in an InP-InGaAsSb double heterojunction bipolar transistor (HBT). The non-ideal collector current is modeled by a non-ideal doping distribution in the base region. Then several consequent non-ideal effects, which have always been neglected in typical HBTs, are studied using Medici device simulator. Moreover, the associated DC parameters of VBIC model are extracted accordingly. The equivalent circuit model is in good agreement with the measured data in I_C-V_CE characteristics.     

Proper choice of the measuring frequency for determining fT of bipolar transistors

The permissible frequencies (f) for measuring f_T are restricted to a certain range characterized by the condition $\text{f}{}_{\mathrm{T}}\text{= /s|β/s| f =}\text{const., i.e.}\text{/s|β/st| }}\text{1}\text{f}$. The boundaries of this range are determined by an analytical calculation and confirmed both by measurements and accurate computer simulations. It is shown that the upper measuring frequency limit f_h of high-speed transistors may drastically be reduced due to the strong influence of parasitic transistor and package parameters (e.g. f_h = 0,1 … 0,2f_Tmax. Therefore the operator must carefully choose his measuring frequency, by use of the relations presented, in order to avoid large errors in determining f_T and the other important transistor parameters (τ_n,C_eb) which can be derived from the current dependence of f_T.     

Transit-time broad-banding of very high bandwidth monolithicp-i-n/HBT optical receivers

The authors show that phase shifts due to electron transit-times in the collector regions of heterojunction bipolar monolithic optical receivers lead to a widebanding of the frequency response or, at worst, circuit instability. Simple quantitative expressions are derived in order to analyze this effect. The dependence of widebanding on the open-loop transistor bias conditions is discussed     

TCAD modeling of NPN-SI-BJT electrical performance improvement through SiGe extrinsic stress layer

The impact of introducing a SiGe stress layer formed over the extrinsic base and adjacent to the intrinsic base of NPN-Si-BJT device on the electrical properties and frequency response has been studied using TCAD modeling. Approximately 42% improvement in f_t and 13% improvement in f_max have been achieved for the strained NPN-Si-BJT device in comparison with an equivalent standard conventional BJT device. In addition to that, an enhancement of the collector current by almost three times has been achieved. The same approach has been applied for NPN-SiGe-HBT device to clarify the impact of the extrinsic SiGe stress on the device's performance using TCAD modeling. Simulation results have shown that applying the SiGe stress layer on the base region of the HBT device is less efficient in comparison with the BJT device, as the SiGe base is already stressed due to the existence of Ge at the base. Approximately 5% improvement in f_max and 3% improvement in f_t have been achieved for the strained HBT device in comparison with an equivalent standard conventional HBT device.     

III–V semiconductors on Si substrates: New directions for heterojunction electronics

Excellent device performance at both d.c. and microwave frequencies has recently been obtained from GaAs based devices grown on Si substrates. In GaAs MESFETs on Si, current gain cutoff frequencies and maximum oscillation frequencies of f_T = 13.3 GHz and f_max = 30 GHz have been obtained for 1.2 μm devices, which is nearly identical to the performance achieved in GaAs on GaAs technology for both direct implant and epitaxial technology. For heterojunction bipolar transistors, current gain cutoff frequencies and maximum oscillation frequencies of f_T = 30 GHz and f_max = 11.3 GHz have been obtained for emitter dimensions of 4 × 20 μm². These results compare with the best reported HBT on GaAs substrates of f_T = 40 GHz and f_max = 26 GHz with much smaller geometry. Given the performance already demonstrated in AaAs on Si devices and the advantages afforded by this technology, the growth of III–Vs on Si promises to play an important role in the future of heterojunction electronics.     

A study of metamorphic HEMT technological improvements: Impact on parasitic effect electrical models

Metamorphic high electron mobility transistor (MHEMT) technology is well adapted to optical high bit rate telecommunication systems. In this context, we propose in this paper a global analysis of this technology in order to verify if it is suitable for system conditions in terms of on-state and off-state breakdown voltages, f_t and f_max, … Our interest concerns the transistor parasitic effects and their impact on the amplifier circuit performances, considering the transistor role in transmitter and receiver modules. We propose new electrical models for each experimentally measured parasitic effect and they could be added to the MHEMT basic models for circuit design.     

Study of RF transistor with submicron T-shaped gate fabricated by nanoimprint lithography

The results devoted to the development of a method for creating an RF transistor, in which a T-shaped gate is formed by nanoimprint lithography, are presented. The characteristics of GaAs p-HEMT transistors have been studied. The developed transistor has a gate “foot” length of the order of 250 nm and a maximum transconductance of more than 350 mS/mm. The maximum frequency of current amplification f _t is 40 GHz at the drain-source voltage V _DS = 1.4 V and the maximum frequency of the power gain f _max is 50 GHz at V _DS = 3 V.     

Physical modeling of lateral scaling in bipolar transistors

The dependence of important transistor characteristics, such as transit frequency, on emitter width and length is modeled on a physical basis. Closed-form explicit analytical equations are derived for modeling the emitter size dependence of the low-current minority charge and transit time, the critical current indicating the onset of high injection in the collector, and the stored minority charge in the collector at high injection. These equations are suited for application in various compact transistor models such as the SPICE Gummel-Poon model (SGPM) as well as the advanced models HICUM and MEXTRAM. As demonstrated by two- and three-dimensional device simulation and measurements, combination of the derived equations with HICUM results in accurate prediction of the characteristics of transistors with variable emitter length and width. As a consequence, the new model makes the conventional transistor library unnecessary and offers bipolar circuit designers the flexibility to use the transistor size that fits the application best     

High-frequency current instabilities in a silicon Auger transistor

In an Auger transistor formed from an Al-SiO₂-n-Si heterojunction with a tunneling-thin oxide layer we have investigated high-frequency instabilities of S-and N-type in the collector current which arise during tunneling injection of hot electrons from the metal into the semiconductor. An Auger transistor is a new type of device in which a metal-insulator heterojunction is used as the wideband semiconductor emitter and the base of the transistor is induced by an electric field in the form of a self-consistent quantum well for holes on the silicon surface. The electrons injected from the metal into the semiconductor with a high kinetic energy (greater than 1 eV) during impact ionization generate electron-hole pairs in the region of the base-collector junction. This disrupts the current balance of the transistor and leads to the appearance of an unstable current of S-or N-type in the collector characteristics (in a circuit with a common emitter). The nature of the instability is connected with the large current gain in an Auger transistor (α>1). Fiz. Tekh. Poluprovodn. 33, 1126–1129 (September 1999)     

Numerical CML switching analyses for heterojunction GaAs/(GaAl)As bipolar transistors

The switching performance of GaAs/Ga_0.7Al_0.3As n-p-n heterojunction bipolar transistors (HBTs) has been investigated for current-mode-logic circuit operation using a hybrid device model composed of numerical one-dimensional transistor and diode models interconnected through resistances corresponding to the real device structure.Switching time is discussed in conjunction with parasitic effects, external circuit conditions and doping profiles.Ultra-high-speed switching of less than 10 ps has been shown to be attainable by scaling the device pattern dimensions down to 1 μm order of magnitude.     

A collector current model for InAlAs/InGaAsSb/InGaAs double heterojunction bipolar transistors with non-ideal effects

A collector current model incorporating electron diffusion in the base and thermionic emission at the abrupt B–E heterojunction is derived and applied to InGaAsSb heterojunction bipolar transistors (HBTs). Parameters extracted from the model include effective base doping concentration, conduction band discontinuity (ΔE_C) at the base-emitter junction, and emitter resistance. The calculated current from the model is consistent with the measured result. It is found that a high collector current ideality factor is resulted from a nonzero ΔE_C and a low effective base doping concentration. Moreover, a nonzero ΔE_C makes the high-injection effect almost invisible in collector current characteristics, even if it actually exists.     

A simple method for separation of the internal and external (peripheral) currents of bipolar transistors

A simple method is described which enables the direct base and collector current of a bipolar transistor each to be separated into an internal and external (peripheral) part. Such a separation is, e.g. a necessary precondition for evaluating the reduction of current gain with decreasing emitter size and, furthermore, for estimating the effective internal base resistance as well as the emitter-current crowding due to the voltage drop across this resistance. The method described is based on very careful measurements of test transistors with different emitter geometries. The approach was experimentally verified with double-implanted high-speed transistors (transit frequency $\text{f}{}_{\mathrm{T}}\text{? 7}\text{GHz}$). For example, an emitter stripe width of about 2 μm leads to the following results: About 32% of the base current but only 9% of the collector current flow outside the emitter area defined by the implantation mask, resulting in a reduction of the common-emitter current gain to about 75% of its internal value.     

Fabrication of Transimpedance Amplifier Module and Post‐Amplifier Module for 40 Gb/s Optical Communication Systems

The design and performance of an InGaAs/InP transimpedance amplifier and post amplifier for 40 Gb/s receiver applications are presented. We fabricated the 40 Gb/s transimpedance amplifier and post amplifier using InGaAs/InP heterojunction bipolar transistor (HBT) technology. The developed InGaAs/InP HBTs show a cut‐off frequency (f_T) of 129 GHz and a maximum oscillation frequency (f_max) of 175 GHz. The developed transimpedance amplifier provides a bandwidth of 33.5 GHz and a gain of 40.1 dBΩ. A 40 Gb/s data clean eye with 146 mV amplitude of the transimpedance amplifier module is achieved. The fabricated post amplifier demonstrates a very wide bandwidth of 36 GHz and a gain of 20.2 dB. The post‐amplifier module was fabricated using a Teflon PCB substrate and shows a good eye opening and an output voltage swing above 520 mV.     

Measurement of the onset of quasi-saturation in bipolar transistors

The onset of quasi-saturation in a bipolar transistor is accompanied by h_FE- and f_T-fall-off and by an increase in h.f. distortion (intermodulation and cross-modulation). We show that the boundary between normal and quasi-saturated operation is easily established experimentally by measuring the l.f. third harmonics of the collector current, as a function of bias voltage and current. Examples are given for ohmic, tepid and hot carrier current flow in the epitaxial collector region.     

SiGe:C HBT transit time analysis based on hydrodynamic modeling using doping, composition and strained dependent SiGe:C carriers mobility and relaxation time

A global additional uniaxial stress ranging from −1 GPa to 1 GPa along different directions has been applied to SiGe HBTs in order to improve the high-frequency performance of these devices. Two transistors have been investigated: a slow one (peak f_T = 110 GHz) and a fast one (peak f_T = 750 GHz). The results from full-band Monte Carlo simulations show that the cutoff frequency of both devices can be improved by more than 30 percent under suitable stress conditions. A spherical-harmonics-expansion simulator is also used to investigate the spatial origin of this improvement, where it is found that the transit times are reduced in all regions (base, collector, emitter).