A simple approach for accurately modeling the threshold voltage of short-channel mosts

We present a theory which models short-channel effects in MOS transistors (MOST). Our approach accounts for the effects of the source and drain depletion regions on the energy band configuration and the effective depletion layer charge under the channel. We derive an equation for low drain bias threshold voltage which accurately predicts the measured threshold on devices ranging in size from very small (1.5 μm) to very large (100 μm) effective channel lengths. The equation reliably predicts the phenomenon of decreasing threshold voltage and body effect observed experimentally from devices of decreasing channel length. The equation is valid for any bulk silicon MOS technology provided that the substrate doping is approximately uniform (i.e. ion-implantation has not been used to adjust the threshold). Our approach can be applied directly to the modeling of the short-channel drain to source current. This application of the theory will be presented in a later paper.     

A new approach to threshold voltage modelling of short-channel MOSFETS

A simple analytical model has been developed to predict the threshold voltage on drain bias dependence of an arbitrarily doped short-channel MOSFET. Based on an analytical solution of the two-dimensional Poisson equation, the potential distribution in the channel depletion region has been derived. The maximum surface field and the minimum surface potential are used to determine the threshold voltage. The influence of drain voltage on threshold voltage has been included by an equivalent shrinkage of the virtual channel length hereafter called “voltage-length transformation”. This simple but general procedure enables us to account for the drain effect and to extend other threshold voltage models derived under assumption of low drain-source voltage. Predictions for threshold voltage have been compared with results of two-dimensional numerical analysis and experimental data. The comparison has been made for a wide variety of doping profiles, channel length, substrate and drain bias, gate oxide thickness and junction depth. Excellent agreement has been obtained down to submicron channel length.     

Modelling the threshold voltage of short-channel silicon-on-insulator MOSFETs

A simple analytical model for the threshold voltage of short-channel, thin-film, fully-depleted silicon-on-insulator MOSFETs is presented. The model is based on the analytical solution for the two-dimensional potential distribution in the silicon film, which is taken as the sum of the long-channel solution to the Poisson equation and the short-channel solution to the Laplace equation. The model shows close agreement with numerical PISCES simulation results. The equivalence between the proposed model and the parabolic model of Young (1989) is also proven.<>     

An analysis of the threshold voltage for short-channel IGFET''s

For short-channel insulated-gate field-effect transistors (IGFET) operating with source-to-substrate reverse bias, the threshold voltage is in general a function of channel length and drain-to-source voltage. It is shown in this analysis that these dependences can be attributed to the two-dimensional distribution of the depletion charges. Starting from two fundamental relations, the overall charge neutrality and the voltage relations based on the energy band diagram, a generalized threshold voltage equation in integral form is derived. A closed-form threshold equation is then obtained using a regional approximation with a simplified piecewise-linear depletion profile. The equation includes as new factors, the channel length, junction depth and drain voltage, and passes to the conventional form for increasing channel length.

The theoretical threshold voltage expression is found to predict the correct tendencies and is shown to be in reasonable agreement with experimental measurements.     

Dependence of the threshold voltage on channel length in BC-mosfet's

The effects of the source-to-drain proximity on the threshold voltage of BC-MOSFET's are considered in this paper. A one-dimensional numerical analysis of Poisson's and the total charge transport equations has yielded the majority carrier concentration along the channel. Utilizing the minimum value of the carrier concentration, n_min nd the channel doping, n_d, a simple expression has been obtained for the magnitude of the difference between the threshold voltages of short and long channel BC-MOSFET's. The results based on this equation are in good agreement with experimental results published in the literature.     

Modeling the short-channel threshold voltage of a novel verticalheterojunction pMOSFET

Analytical modeling of the threshold voltage of a Si_1-xGe_x/Si heterojunction pMOSFET has been performed using a quasi-two-dimensional (quasi-2-D) approach for the calculation of the potential. It is shown that the use of Si_1-x Ge_x in the source region leads to an improvement in the short-channel behavior of deep submicron pMOSFETs. The V_T roll-off can be substantially decreased by introducing a material dependent barrier between source and channel. Furthermore it will be proven that this advantage will become stronger when channel lengths are decreased toward the deep submicron regime     

A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.     

Simple model for threshold voltage in a short-channel IGFET

The threshold voltage of a short-channel IGFET can be expressed, in relation to that for a long-channel device, asV_{T} = V_{TLC} - alpha - betaV_{DS}. This behavior is deduced from a charge injection model and is verified both by two-dimensional numerical simulations and by actual threshold data.     

Reverse short-channel effects on threshold voltage in submicrometersalicide devices

A reverse short-channel effect on threshold voltage caused by the self-aligned silicide process in submicrometer MOSFETs is reported. A physical model of lateral channel dopant redistribution due to the salicide process is proposed. The injection of vacancies and lattice strain during TiSi₂ formation causes defect-enhanced boron diffusion which results in a nonuniform lateral channel dopant redistribution and hence a threshold increase in short-channel devices. In addition to the small gate edge birds beak and the nonuniform oxidation-enhanced diffusion (OED) redistribution of channel dopant due to the polysilicon gate reoxidation, the self-aligned Ti silicide process can be major cause of the observed reverse short-channel effect in submicrometer MOSFET devices     

Flat-band voltage dependence on channel length in short-channel threshold model

This paper describes a modified short-channel threshold model that incorporates the flat-band voltage dependence on the channel length. Results obtained from the threshold voltage measurement on n-channel MOSFET's before and after total dose radiation are in good agreement with the proposed model.     

A simple model for threshold voltage of surrounding-gate MOSFET's

We propose a threshold voltage model for surrounding-gate MOSFETs. The model treats the ends and the double-gate regions of the channel as separate devices operating in parallel. The threshold voltage for the full device is obtained as the perimeter-weighted sum of the threshold voltages of the two parts enabling simple analytic threshold models to be used. Short channel effects and drain-induced barrier lowering are also modeled in this manner     

A simple punchthrough voltage model for short-channel MOSFET's with single channel implantation in VLSI

Based on the step-profile approximation and geometrical analysis, the punchthrough voltage of short-channel enhancement n-channel MOSFET's with single channel implantation has been derived by defining a punchthrough depth. The punchthrough depth, which represents the distance of the two-dimensional potential ridge from the SiO2-Si interface, is calculated by the surface potential of the punchthrough point. Therefore, the derived punchthrough voltage model is then analytically expressed in terms of device geometries and implant parameters. Comparisons between the developed model and the experimental devices have been made and excellent agreement has been obtained.     

Analytical threshold voltage model for ultrathin SOI MOSFETsincluding short-channel and floating-body effects

Short-channel effects (SCE) in ultrathin silicon-on-insulator (SOI) fully depleted (FD) MOSFETs are analyzed and an analytical model for threshold voltage, including the kink effect, is presented. The proposed model accounts for (1) a general nonuniform channel doping profile, (2) the drain-induced V_th- lowering enhancement resulting from the interaction of (a) impact ionization, (b) floating-body, and (c) parasitic-bipolar effects. Good agreement between the proposed model and experimental data is demonstrated. Impact ionization and floating-body effects dominate V_th lowering for drain voltages larger than V_dk≃B_i.λ_i/3, where B_i is the impact ionization coefficient, and λ_i is the impact ionization length, a structural parameter which, for a single-drain SOI MOSFET, coincides with the SCE characteristic length λ     

A new 2-D model for the potential distribution and threshold voltage of fully depleted short-channel Si-SOI MESFETs

A new two-dimensional (2-D) analytical model for the threshold voltage of a fully depleted short-channel Si-MESFETs fabricated on the silicon-on-insulator (SOI) has been presented in this paper. The 2-D potential distribution functions in the active layer of the device is approximated as a parabolic function and the 2-D Poisson's equation has been solved with suitable boundary conditions to obtain the bottom potential at the Si/oxide layer interface. The calculations have been carried out for both uniform and nonuniform doping profiles in two dimensions. The minimum bottom potential is used to monitor the drain-induced barrier lowering effect and consequently an analytical expression for the threshold voltage of the device has been derived. The numerical results for the bottom potential and threshold voltage considering a wide range of device parameters have also been presented. The model has been compared with the simulated results obtained by using the ATLAS Device Simulation Software to show the validity of the proposed model. For uniform doping profile, the numerical results have also been compared with the reported data in the literature and a good agreement is observed among the three. The proposed model is simple and easy to understand the behavior of the fully depleted short-channel SOI-MESFETs as compared to the other models reported in the literature.     

A simple model of the threshold voltage of short and narrow channel MOSFETs

Simple but reasonably accurate equations are proposed which describe the behavior of threshold voltage for short and narrow-channel MOSFETs, for low drain-source voltages.

It will be shown that good agreement is obtained between the model, experiment and two dimensional calculations, for channel lengths and widths as small as 1 2 μm. Moreover, by careful analysis of the model results, some new properties of the threshold voltage of small size devices can be derived.     

Threshold voltage theory for a short-channel MOSFET using a surface-potential distribution model

A detailed expression of the threshold voltage for a short-channel MOSFET is derived from a model of surface-potential distribution under the gate using a relationship of surface-channel charge neutrality. The theory is compared with the measured threshold voltages. The theoretical curves for threshold voltage over a wide range of drain and backgate voltage are in good agreement with experimental results. It is shown for a MOSFET having a channel length less than 2 μm that the body-bias constant increases as the drain voltage increases. The theory also predicts that the increase in backgate voltage leads to the reduction in short-channel effect for the shorter-channel case.     

A simple punchthrough model for short-channel MOSFET's

Punchthrough currents impose severe limitations on the minimum channel length and leakage currents of scaled MOS transistors. A simple model is proposed to calculate the low-level punchthrough characteristics. Taking into account the two-dimensional geometrical effects, this model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters, and the gate, drain, and substrate bias. Experiments on devices with substrate dopings 6 × 10¹⁴and 6.6 × 10¹⁵cm^-3and channel lengths from 1 to 2 µm show good agreement with the theory.     

Stable threshold voltage extraction using Tikhonov's regularization theory

We propose a new threshold voltage extraction with stability based on Tikhonov's regularization theory. It suppresses the instability of the transconductance change method and gives mathematically exact solution. Following the mathematical derivation, we convert the procedure into the MATLAB programming for users' convenience. Finally, the proposed method extracts the threshold voltage close to the physically meaningful one which means the gate-to-source voltage where /spl phi//sub s/=2/spl phi//sub f/+V/sub SB/. To confirm the proposed one, we compare it with others such as the linear extraction and the normalized mutual integral difference method. It was found that the proposed one extracted the physically meaningful threshold voltage very closely. Moreover, it is also observed that there is a high correlation between the proposed and the normalized mutual integral difference method.     

A simple analytical threshold voltage model of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs

For the first time, a simple and accurate analytical model for the threshold voltage of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs is developed by solving the two-dimensional (2-D) Poisson equation. In the proposed model, the authors have considered several important parameters: 1) the effect of strain (in terms of equivalent Ge mole fraction); 2) short-channel effects; 3) strained-silicon thin-film doping; 4) strained-silicon thin-film thickness; and 5) gate work function and other device parameters. The accuracy of the proposed analytical model is verified by comparing the model results with the 2-D device simulations. It has been demonstrated that the proposed model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, i.e., with increasing equivalent Ge concentration. The proposed compact model can be easily implemented in a circuit simulator.