Accelerated stress testing of a-Si:H pixel circuits for AMOLED displays

Electronics reliability testing is traditionally carried out by accelerating the failure mechanisms using high temperature and high stress, and then predicting the real-life performance with the Arrhenius model. Such methods have also been applied to organic light-emitting diode (OLED) testing to predict lifetimes of tens of thousands of hours. However, testing the active matrix OLED thin-film transistor (TFT) backplane is a unique and complex case where standard accelerated testing cannot be directly applied. This is because the failure mechanism of pixel circuits is governed by multiple material and device effects, which are compounded by the self-compensating nature of the circuits. In this paper, we define and characterize the factors affecting the primary failure mechanism and develop a general method for accelerated stress testing of TFT pixel circuits in a-Si AMOLED displays. The acceleration factors derived are based on high electrical and temperature stress, and can be used to significantly reduce the testing time required to guarantee a 30 000-h display backplane lifespan.     

Low-Field Time-Dependent Dielectric Integrity

A major contributor to reliability failures in integrated circuits has been the failure of dielectrics under operating stress. This paper summarizes extensive studies carried out on many manifestations of dielectric integrity failure. The outcome is a single model used to predict failure from data obtained in accelerated testing. The model contains the effect of temperature and applied voltage on the tendency to fail as well as the breakdown of the region subject to stress.     

基于加速环境的可靠性指标验证试验

首先进行了电子产品失效模型的理论研究,并利用加速退化试验技术而研究了某通信产品失效机理一致的应力范围,通过对试验数据进行的统计分析,计算出失效机理一致情况下的激活能。在可靠性指标验证的试验研究中,将试验样品分成若干组分别进行恒温加速验证试验,并将试验结果与现场统计数据进行比较,最终确定产品的MTBF。     

Towards prognostics and health monitoring: The potential of fault detection by piezoresistive silicon stress sensor

A piezoresistive silicon based stress sensor has been demonstrated successfully as an effective tool to monitor the stresses inside electronic packages during various production processes. More recently, the sensor has been evaluated as a sensor for Prognostics and Health Monitoring (PHM) systems. This paper presents a systematic approach that evaluates its performance from the perspective of failure mode detection. A detailed Finite Element method (FEM) model of existing test vehicles is created. The test vehicle consists of six DPAK (Discrete Package) power packages and three stress sensors. The results of simulation are verified by the signals obtained from the stress sensor as well as the supplementary warpage measurements. After inserting various failure modes into the model, statistical pattern recognition algorithms are implemented for fault detection and classification. The proposed technique can identify detectable failures during reliability testing by utilizing the database of stress sensor responses for healthy and unhealthy state. Thus, the results establish a baseline for the applicability of the piezoresistive stress sensor for an on-line monitoring PHM methodology.     

TiN and TaN diffusion barriers in copper interconnect technology: Towards a consistent testing methodology

The present status of work on diffussion barriers for copper in multilevel interconnects is surveyed briefly, with particular emphasis on TiN and TaN, and silicon dioxide as the interlayer dielectric. New results are presented for these materials, combining thermal annealing and bias temperature stress testing. With both stress methods, various testing conditions are compared using capacitance-vs-voltage (C-V) and leakage current-vs-voltage (I-V) measurements to characterize the stressed samples. From an evaluation of these data and a comparison with other testing approaches, conditions for a consistent testing methodology of barrier reliability are outlined.     

An improved reliability model for Si and GaN power FET

The existing standard reliability models for power devices are not satisfactory and they fall short of predicting failure rates or wear-out lifetime of semiconductor products. This is mainly attributed to two reasons; the lack of a unified approach for predicting device failure rates and the fact that all commercial reliability evaluation methods relay on the acceleration of one dominant failure mechanism. Recently, device reliability research programs are aimed to develop new theoretical models and experimental methods that would result a better assessment of the device lifetime as well as point out on the dominating failure mechanism for particular operating conditions. A new model, named Multi failure mechanism, Overstress Life test (MOL) has been introduced and posed a better understanding of the dominating failure mechanisms under various stressed conditions in advanced FPGA devices (for 45 and 28 nm technologies). In this work we present, for the first time, the implementation of the MOL model to investigate the reliability of silicon power MOSFET and GaN power FET devices. Both, LTSpice simulation and experimental data are presented for a test circuit of a ring oscillator, based on CMOS-FET, NMOS-FET, PMOS-FET and N-channel e-GaN FET. The monitored data was acquired in-situ in form of the ring frequency or Vds values that enabled to assess the lifetime and determine the dominating mechanism during accelerated wearout by temperature, applied bias voltage, thermal cycling, gamma and electron irradiation. Moreover, in the case of GaN devices, RDS-On monitoring circuit has also been operated during thermal cycling of the tested component and the acceleration factor was derived for various operational parameters.     

SOI电路可靠性筛选技术及失效机理研究

可靠性筛选是提高电子产品良率的重要技术手段。针对绝缘体上硅（SOI）技术日益广泛的应用,通过大量实验研究了SOI电路的常用筛选试验,并对失效样品进行了相应的失效机理研究。首先讨论了SOI电路失效模式和筛选方法之间的关系;其次,针对三款SOI电路分别开展了老炼应力、高温贮存及恒定加速度试验来进行可靠性筛选;最后,利用光发射显微镜、扫描电子显微镜、聚焦离子束和激励源诱导故障测试等失效分析手段,对失效样品进行了失效模式及机理分析,揭示了失效根源,为改进工艺、提高SOI电路可靠性提供了依据。     

Qualification of plastic encapsulated microcircuits (PEM) for avionicsBased on ``Plastic Encapsulated Microcircuits (PEM) Qualification Testing'''', by J. A. Scalise, which appeared in the Proceedings of the 46th Electronic Components and Technology Conference, Orlando, FL, U.S.A., 28–31 May 1996, pp. 392–397. © 1996 IEEE.

Microcircuit package qualification testing is used to establish the reliability of integrated circuit processes and devices as they relate to part packaging. This paper presents the results of package qualification tests conducted on plastic encapsulated microcircuits (PEMs) and plastic discrete devices (diodes, transistors) used in avionics applications. Highly accelerated stress test (HAST) and temperature cycle (TC) test results, including part failure mechanisms and associated failure rates, are provided. A variety of plastic package styles and integrated circuit functions have been tested. Examples of package styles tested include small outline (SO), plastic leaded chip carrier (PLCC), thin small outline package (TSOP), plastic quad flat package (PQFP) and plastic dual-in-line (PDIP).Manufacturers' devices have been evaluated and various plastic compounds have been compared to determine which provide optimum reliability. The testing showed that package qualification performance of PEMs is affected by type of compound, passivation (including die coat) and die size. HAST failures are caused by moisture penetration of the package while temperature cycle failures result from coefficient of thermal expansion (CTE) mismatch effects.     

Electromigration in thin-films for microelectronics

Electromigration (EM) is one of the major concerns for the development of ULSI divices, but not all the aspects of the phenomenon are presently well understood. In this paper well established results and unsolved problems are reviewed and discussed.First, the physical model and in particular the influence of the mechanical stress on EM is considered. Then, the various techniques used to characterize electromigration are analyzed, making distinction between traditional techniques (median time to failure technique and resistometric methods) and more recently developed methods (high-resolution resistometric techniques and low-frequency noise measurement), also considering the fast techniques used for metallisation testing in the industrial environment. Finally, a section is devoted to the problem of test-structure and test-procedure standardisation in EM experiments.     

A Survey on Testing and Monitoring Methods for Stator Insulation Systems of Low-Voltage Induction Machines Focusing on Turn Insulation Problems

A breakdown of the electrical insulation system causes catastrophic failure of the electrical machine and brings large process downtime losses. To determine the conditions of the stator insulation system of motor drive systems, various testing and monitoring methods have been developed. This paper presents an in-depth literature review of testing and monitoring methods, categorizing them into online and offline methods, each of which is further grouped into specific areas according to their physical nature. The main focus of this paper is on testing and monitoring techniques that diagnose the condition of the turn-to-turn insulation of low-voltage machines, which is a rapidly expanding area for both research and product development efforts. In order to give a compact overview, the results are summarized in two tables. In addition to monitoring methods on turn-to-turn insulation, some of the most common methods to assess the stator's phase-to-ground and phase-to-phase insulation conditions are included in the tables as well.      

数字图像相关用于印刷电路板全场微应变的测量

提出了利用数字图像相关技术测量印刷电路板全场微应变的方法,用于评估电路板由应力所导致的失效风险,克服传统实验测试方法不能有效测量全场应变以及难以给出应变集中区域的不足。设计了基于三维数字图像相关技术和应力加载策略的实验方法,通过所获得的全场主应变分布及局部区域内应变历史曲线来评估电路板的失效风险。实验结果表明,所提出的电路板微应变测量方法的重复性优于100 ,能够有效地获得电路板全场的微应变分布,尤其是能够直观地显示电路板应变超过额定值的区域分布,为改进电路板设计、降低电路板失效风险和保护电子元器件的安全提供了重要的实测数据。     

Development of a high-resolution quartz resonator force and weight sensor with increased reliability

Test-analyze-and-redesign method is employed to develop a quartz crystal resonator (QCR) force and weight sensor with increased reliability for batch production. The sensor, which mainly consists of a QCR and a metal diaphragm structure, has the advantages of high resolution, digital output, and low cost. The failure mechanism of the single-diaphragm QCR sensor has been uncovered by experiments aiming at providing insight into the failure factors. In order to eliminate the failure stress and improve reliability, the sensor has been redesigned based on failure analysis results by designing a double-diaphragm structure. Life testing experiments for validating the effect of the corrective action show that reliability has been improved five times, and after redesign, the reliability satisfies the requirement of practical use. Accelerated life testing is performed to find acceleration factors and development stresses for batch production.     

关于PCBA板使能控制引脚开路的失效分析

介绍了某通信设备中PCBA板使能控制引脚开路的失效分析结果。通过采用外观检查、X射线透视、切片分析、可焊性测试和镀层厚度测量,以及实验验证等一些列技术手段,确定了PCBA板上电源模块功能失效的根本原因,即在高温作用下PCB内层发生树脂收缩现象,产生的内应力使内层连接开路。     

A reliability model for SAC solder covering isothermal mechanical cycling and thermal cycling conditions

This paper presents an alternative to the use of energy-based methodologies for life cycle predictions of solder interconnects. Isothermal mechanical cycling testing has been conducted using joint-scale solder samples on a novel testing apparatus. The test data shows that work as a single parameter is insufficient in predicting failure; nor does the inclusion of cyclic frequency and mean temperature improve work-based methodologies. Here, a novel semi-empirical approach is presented in which stress, strain, strain rate and temperature are individually treated to create a model capable of predicting material behaviour under arbitrary cyclic loading conditions. The model constants are fitted to the results of the isothermal mechanical cycling tests, using load drop as a measure of damage. The calibrated model is then employed to predict the failure of a BGA device under thermal cycling. The modelling results show state-of-the-art agreement with the test data and superiority over Morrow model constants from literature that have been applied to this data set.     

A grain structure based statistical simulation of electromigration damage in chip level interconnect lines

Reliability assessment of chip level interconnects is based on accelerated testing at a higher temperature and a larger current density than expected in service conditions. The critical parameters needed to extrapolate accelerated test data to service conditions are the activation energy, Q, and the current density exponent, n. Although current density exponents and activation energies are well known for the elemental processes (like void nucleation due to electromigration (EM) generated stress), there is no consensus on which apparent activation energy or current density exponent values would be applicable in reliability estimates for realistic line structures. Here, we first review our EM simulation tool. We then apply the EM simulation tool to statistical life time analysis of realistic-like line structures generated by a Monte-Carlo algorithm. For a given grain structure distribution, the stress evolution along the line is simulated, letting voids nucleate at the sites where the stress exceeds a critical level, and the nucleated voids are then allowed to grow till the largest one reaches the preset critical size, resulting in a ‘failure’ of the particular line. By repeating this process for various current densities and temperatures, it becomes possible to extract the apparent activation energies and current density exponents from the simulation data.     

温度湿度对产品的影响分析

环境应力试验是产品质量鉴定及保证不可缺少的条件之一。论述了温度、湿度及冷热冲击等不同的环境应力对产品的影响。试验证明,通过必要的环境应力试验,可以减少产品的循环,去除缺陷产品,降低产品故障率。     

可靠性仿真试验及其在雷达研制中的应用

可靠性仿真试验是基于故障物理原理和计算机技术,利用计算机仿真分析软件,对雷达等电子设备进行数字模型可靠性分析和计算的过程。通过软件在电子样机上施加产品所经历的载荷历程,分解到产品的基本模块上,进行应力分析和应力损伤分析,从而找出产品的设计薄弱环节;通过仿真预计产品的失效时间分布并分析,指导和辅助可靠性设计优化;通过可靠性仿真量化评估,比较设计方案,为可靠性综合评价提供支持。研究表明：可靠性仿真试验缩短了雷达研制周期,提高了雷达可靠性水平。     

System-level reliability assessment of mixed-signal convergent microsystems

The next-generation convergent microsystems, based on system-on-package (SOP) technology, require up-front system-level design-for-reliability approaches and appropriate reliability assessment methodologies to guarantee the reliability of digital, optical, and radio frequency (RF) functions, as well as their interfaces. Systems approach to reliability requires the development of: i) physics-based reliability models for various failure mechanisms associated with digital, optical, and RF Functions, and their interfaces in the system; ii) design optimization models for the selection of suitable materials and processing conditions for reliability, as well as functionality; and iii) system-level reliability models understanding the component and functional interaction. This paper presents the reliability assessment of digital, optical, and RF functions in SOP-based microsystems. Upfront physics-based design-for-reliability models for various functional failure mechanisms are presented to evaluate various design options and material selection even before the prototypes are made. Advanced modeling methodologies and algorithms to accommodate material length scale effects due to enhanced system integration and miniaturization are presented. System-level mixed-signal reliability is discussed thorough system-level reliability metrics relating component-level failure mechanisms to system-level signal integrity, as well as statistical aspects.     

Extensive investigations of temperature influence on barrier integrity during reliability testing

Investigation of stress migration phenomena is one of the key aspects to characterize metallization reliability. Typical test methodologies are investigations of resistance shifts at wafer-level or package-level temperature storage tests under a temperature range between 150 °C and 275 °C. During these tests a very limited resistance increase dependent on the test structure is allowed. Most recently we encounter unusual resistance shift at the highest stress temperature which did not yield classical stress voiding detectable by failure analysis. We found changes in barrier integrity explaining the resistance shift by barrier oxidization. This has been verified by specially prepared material as well as extensive failure analysis investigation.     

A methodology for the calculation of stress migration in die-level interconnects

An analytic methodology is presented for the examination of stress migration in the built up interconnect structures on integrated circuit die. The methodology uses finite element analysis combined with a presumed diffusion mechanism to define a vacancy accumulation site and to characterize the flux of vacancies. This physics-based approach accounts for the effects of time, temperature, material systems and interconnect geometry on stress migration. The method should be generally applicable to a wide range of interconnect structures and will find utility in the design of stress migration tolerant designs as well as in failure analysis.Through examples, stress migration within copper lines and vias with low-k and SiO₂ dielectrics is examined. The methodology predicts increased vacancy fluxes with increases in exposure time, line width and temperatures within the range studied. A fundamental mechanism suggesting heightened vacancy fluxes with a low-k dielectric over a SiO₂ dielectric is described. Finally, the methodology is exercised to demonstrate that the apparent activation energy obtained through stress migration testing of built up interconnect structures may not correspond with the governing diffusion mechanism.