Static RAM cell for ternary logic

A novel CMOS static RAM cell for ternary logic systems is described. This cell is based on the lambda diode. The operation of the cell has been simulated using the SPICE 2G program. The results of the simulation are given.     

A knowledge-based test generator for standard cell and iterative array logic circuits

The use of Prolog for test generation is discussed and an implementation in Prolog of an automatic test generator, Protean, for stuck-at faults in scan-designed standard cell VLSI circuits and iterative logic arrays is described. Protean comprises a cell test generator, which generates test knowledge and propagation characteristics for cells, and a hierarchical test generator, which uses this high-level test knowledge in conjunction with low-level structural information to generate tests for the circuit.<>     

CMOS logic cell switching speed thermal characterisation

A study of the switching speed performance of basic CMOS logic cells in the (junction) temperature range 25?250°C is reported. Experimental measurements for capacitively loaded inverters and NAND gates of two standard 4 ?m CMOS processes are compared to theory and to SPICE2G. 6 simulations. It is found that, to a good approximation, a simple delineation factor (lying between 0.004 and 0.006/deg C in this study), applied to the average gate delay at a given temperature, correctly predicts this parameter. Logic cells are thereby typically found to be up to 65% slower at 250°C than they are at room temperature.     

A BiCMOS wired-OR logic

This paper proposes a BiCMOS wired-OR logic for high-speed multiple input logic gates. The logic utilizes the bipolar wired-OR to circumvent the use of a series connection of MOS transistors. The BiCMOS wired-OR logic was found to be the fastest compared with such conventional gates as CMOS NOR, BiCMOS multiemitter logic and CMOS wired-NOR logic, when the number of inputs was more than four and the supply voltage was 3.3 V. The BiCMOS wired-OR logic was also determined to be the fastest of the four when the fan-out number was below 20 and the number of inputs was eight. In addition, the speed was more than twice as faster when the fan-out number was less than 10. The BiCMOS wired-OR logic was applied to a 64-b 2-stage carry look-ahead adder, and was fabricated with a 0.5-μm BiCMOS process technology. A critical path delay time of 3.1 ns from an input to a sum output was obtained at the supply voltage of 3.3 V. This is 35% faster than that of conventional BiCMOS adders     

Compatible cell connections for multifamily dynamic logic gates

Dynamic logic is an alternative way of making logic circuit cells and numerous techniques have been developed to take advantage of its unique characteristics. Particularly, techniques such as the true-single-phase-clock (TSPC) have been used very successfully for fast and low-power applications. However one cannot synthesize dynamic logic gates with the same ease as static gates. One reason is there are no simple rules to connect the many circuit types of dynamic gates to static gates. This paper addresses the problem of finding connection rules for a given set of gate types. The fundamental cell circuit types for dynamic logic gates are analyzed first together with static logic gates. A common set of principles of operation and connections is then identified and later applied to discover which are the feasible connections between cell circuit types identified.     

A new current-routing logic counter

The integrated synchronous 2³-counter described below uses binary current-routing logic stages with a minimum number of components, crossings and collector islands. Maximum toggle frequency is 60 MHz at 12 mW per stage. With few interconnections between identical chips a synchronous 2⁹-counter can be realized.     

A fuzzy logic inference processor

A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 μm CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-mass defuzzification, may be computed in 2 μs     

A new RTD-FET logic family

We describe a new family of clocked logic gates based on the resonant-tunneling diode (RTD). Pairs of RTDs form storage latches, and these are connected by networks consisting of field-effect transistors (FETs), saturated resistors, and RTDs. The design, operation, and expected performance of both a shift register and a matched filter using this logic are discussed. Simulations show that the RTD circuits can achieve higher performance in terms of speed and power in many signal processing applications. Compared to circuits using III-V FETs alone, the RTD circuits are expected to run nearly twice as fast at the same power or at the same speed with reduced power. Compared to circuits using Lincoln Laboratory's fully depleted silicon-on-insulator CMOS, implementation using state-of-the-art RTDs should operate five times faster when both technologies follow the CMOS design rules     

A logic nanotechnology featuring strained-silicon

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.     

一种基于标准逻辑单元的GALS异步封装电路

基于点对点GALS模型,给出了异步封装电路的信号状态转换图(STG),基于Petrify设计了一种基于标准逻辑单元的GALS异步封装电路,包括同步/异步接口电路、具有分频及暂停功能的局部时钟等设计.由于所设计的异步封装电路具有不存在延时器件、没有使用特殊的异步逻辑单元等特点,所以论文基于两个同步计数器实现了GALS点对点模型进行仿真和FPGA验证,结果显示了整个异步封装及其GALS系统性能的正确性.     

A four-variable programmable universal logic module using digital summation threshold logic gates

Combining the concepts of programmable logic arrays (PLAs) and conventional universal logic modules (ULMs) a new type of programmable ULM for four variables has been proposed. The realization is based on the digital summation threshold logic (DSTL) gates, a cellular array for realizing threshold logic functions.     

A successive approximation logic frequency-to-code converter

A new frequency-to-code converter (fDC) circuit in which an input frequency fiis processed by successive approximation logic (SAL) to generate a proportional digital number is described in this letter. Several ingenious subcircuits plus the conventional sequencer clocked by the input hertz constitute the SAL fDC. Conversion time is equal to nTiwhere n is the number of bits in the output digital word and Tiis the period of the input hertz.     

一种模糊时态描述逻辑

针对现实生活中信息的时间性和模糊性,在模糊描述逻辑和时态逻辑的基础上,提出了一种模糊时态描述逻辑FTDL,并给出了其语法和语义的相关说明。与模糊描述逻辑FALC相比,FTDL的提出为语义Web服务的建模和推理提供了一种有效的途径。     

A proposed distributed Josephson logic circuit

A new Josephson logic circuit is proposed with spatially distributed inputs and outputs. It is uniquely suited to picosecond functional logic arrays, memory peripheral circuits, and other applications requiring large distributed fan-in.     

Control logic and cell design for a 4K NVRAM

A high-density 4K 5-V-only nonvolatile static RAM has been designed using a wafer stepper HMOS I FLOTOX E/SUP 2/PROM technology. Normal SRAM read/write operations and parallel data transfer between SRAM and E/SUP 2/PROM array are possible. On-chip high-voltage regulation and generation, junction leakage control, and self-timing circuitry ensure full military temperature operation. Power-down store lockout protection and power-up automatic recall are featured.     

An efficient current-based logic cell model for crosstalk delay analysis

Logic cell modelling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behaviour of CMOS cells with respect to the voltage signal at their input and output pins. A current-based model for CMOS logic cells is presented, which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits. Existing current source models are expensive and need a new set of Spice-based characterisation, which is not compatible with typical EDA tools. In this article we present Imodel, a simple nonlinear logic cell model that can be derived from the typical cell libraries such as NLDM, with accuracy much higher than NLDM-based cell delay models. In fact, our experiments show an average error of 3% compared to Spice. This level of accuracy comes with a maximum runtime penalty of 19% compared to NLDM-based cell delay models on medium-sized industrial designs.     

A general modified universal logic module

The concept of building an n-variable universal logic module (ULM-n) is considered, based on a single building block, unlike that of Banks and Majithia, who suggested two building blocks, namely, ULM-2 and ULM-3. The input control functions have been kept the same, namely, 2-bit binary codes. This basic building block is then used for the synthesis of switching functions.     

A DC-powered Josephson logic family that uses hybrid unlatchingflip-flop logic elements (Huffles)

This paper describes the development of a dc-powered Josephson logic family that uses hybrid unlatching flip-flop logic elements (Huffles). The Huffle circuit used in this study is modified by adding a parallel resistor to the original Hebard-type Huffle circuit. Analysis of the circuit's operation shows that the undesirable hung-up phenomena are prevented by this modification. Based on the result of the analysis, the circuit's parameters are derived and a typical operating margin of ±26% is obtained. Besides AND/OR operations using a threshold logic operation, two-input exclusive OR (XOR), two-input multiplexor (MUX), and three-input majority (MAJ) operations are realized using a Huffle gate in which 2-Josephson-interferometers (2JI) in the standard Huffle gate are replaced by stacked-2JI's. Thus, a Huffle logic family, formed from NOT, AND, OR, XOR, MUX, MAJ, and flip-flop (FF), are constructed. By using this Huffle logic family, a 6-b arithmetic logic operating unit (ALU), a 6-b analog-to-digital converter (ADC), and a 6-b gray-to-binary converter (GBC) have been successfully operated. During high-speed testing, a 1-b comparator was operated up to an input bandwidth of 6 GHz