CMOS LC-oscillator phase-noise analysis using nonlinear models

In this paper, a second-order stochastic differential equation is used as a tool for the analysis of phase noise in a submicron CMOS LC oscillator. A cross-coupled topology typical of integrated CMOS designs is considered. Nonlinear limiting and mobility degradation effects in the circuit are modeled and used to predict the statistics of the random amplitude and phase deviations in terms of design variables. Assuming Gaussian noise disturbances and describing the phase noise as a random diffusion process, the average phase-noise power spectrum is derived and its accuracy verified with measurement and simulation results. Calculations for phase noise arising from stationary tank noise, nonstationary channel thermal noise, and flicker noise are discussed. The analysis is used to emphasize the fundamental power/performance tradeoff associated with compensation of tank losses via adjustments in the power supply and device size.     

Minimizing Phase Noise Variation in CMOS Ring Oscillators

The variation of phase noise across the frequency of operation of a CMOS ring oscillator is described analytically. The delay element of the ring oscillator considered comprises of a source-coupled differential pair with an active load element. In this circuit topology where the frequency of oscillation is varied by changing the resistance of the load, theory derived in this work predicts that phase noise will remain constant if constant output swing is maintained. Such an oscillator is designed in a 0.5 m CMOS process and the simulation results verify the theoretical analysis. Consequently, an oscillator design methodology is provided that dramatically reduces the phase noise optimization problem to just one frequency within the oscillator's output frequency range.     

RF Oscillator Based on a Passive RC Bandpass Filter

A passive RC bandpass filter (BPF) based voltage-controlled-oscillator (VCO) operating at 2.5 GHz is presented. In GHz frequency range, a preferred type of an oscillator is either an LC oscillator or a ring oscillator. An LC oscillator exhibits an excellent phase noise performance while its fabrication cost is expensive due to the inductors. On the other hand, a ring oscillator can be built with standard CMOS devices resulting in a cheap fabrication cost. However, it has a poor phase noise and jitter performance and is sensitive to power supply noise. This paper proposes a RC BPF-based oscillator. Its property is closer to a LC oscillator rather than a ring oscillator and, as a result, improves the jitter performance due to power supply noise. Also, it can be fabricated in a standard CMOS process since there is no inductor. To prove the proposed concept, a RC BPF-based oscillator was designed and fabricated in a standard 0.13-$mu{hbox {m}}$ CMOS technology. An operating frequency of 2.5 GHz and phase noise of $-$ 95.4 dBc/Hz at 1$~$MHz offset was measured. Power consumption was 2.86 mW from a 1.3$~$ V supply voltage.      

使用新注入锁定技术的低相位噪声正交振荡器

提出了一种利用新注入锁定技术的低相位噪声正交振荡器,激励信号直接注入子谐波振荡器的共源连接点.原理上,正交振荡器的相位噪声性能会比子谐波振荡器的相位噪声性能好.该正交振荡器已经采用0.25μmCMOS工艺实现,测试结果表明该正交振荡器的振荡频率约为1.13GHz,在偏离振荡频率1MHz处的相位噪声约为-130dBc/Hz.该振荡器采用2.5V电源电压,消耗的电流约为8.0mA.     

A study of phase noise in CMOS oscillators

This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency multiplicative noise, and low-frequency multiplicative noise, are identified and formulated. Based on the same concepts, a CMOS relaxation oscillator is also analyzed. Issues and techniques related to simulation of noise in the time domain are described, and two prototypes fabricated in a 0.5-μm CMOS technology are used to investigate the accuracy of the theoretical predictions. Compared with the measured results, the calculated phase noise values of a 2-GHz ring oscillator and a 900-MHz relaxation oscillator at 5 MHz offset have an error of approximately 4 dB     

5-GHz Oscillator Array With Reduced Flicker Up-Conversion in 0.13-$muhboxm$CMOS

Voltage supply scaling in CMOS processes requires lower inductance and higher capacitance in conventional LC oscillators. Forcing several LC oscillators to run in phase is a valuable means of achieving the wanted phase noise with practical values of inductances and capacitances. However, in-phase oscillator arrays suffer from the up-conversion of transistors' flicker noise, in the presence of oscillator mismatches. A multitank oscillator topology is proposed, which has superior tolerance to mismatches and removes this mechanism of noise degradation. In order to assess such topology, an 802.11 a-compliant VCO with four coupled oscillators has been designed in a 0.13-mum CMOS technology. A phase noise better than -120 dBc/Hz at 1-MHz offset has been achieved along the 4.7-5.9-GHz tuning range     

Dual-band low-phase-noise LC-QVCO using series coupling and switched biasing techniques

An LC-tank quadrature voltage-controlled oscillator (QVCO) is proposed to achieve frequency-band reconfigurability and low phase noise. In this work, phase noise contributed by the 1/f noise of coupling transistors and tail transistors is noticeably reduced when series coupling and switched biasing techniques are simultaneously adopted. The proposed QVCO was implemented in 0.25-μm triple-well CMOS process for K-PCS and WCDMA bands. Measured results showed a phase noise of ?117 dBc/Hz at an offset of 1 MHz and a phase-noise figure-of-merit of ?172 dBc/Hz while consuming 8.13 mA from a 2-V power supply.     

Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages

A method to minimize the supply sensitivity of a CMOS ring oscillator is proposed through joint biasing of the supply and the control voltage. The technique can supplement a number of common supply rejection techniques and can be exploited to compensate for the noise coupling caused by the parasitic capacitance in the loop filter of a phase-locked loop (PLL). The proposed CMOS ring oscillator is designed and implemented with a charge-pump based PLL in 65-nm technology to demonstrate the robustness against the supply fluctuation. Taking advantage of the negative static supply sensitivity of the ring oscillator with proper combination of the bias voltages, the rms jitter of the 5.12-GHz output clock is reduced from 6.41 ps to 2.38 ps while subject to supply noise at 90 MHz.      

Phase-Noise Reduction of X-Band Push–Push Oscillator With Second-Harmonic Self-Injection Techniques

A low phase-noise X-band push-push oscillator using proposed feedback topology is presented in this paper. The oscillator core was implemented in a 0.18-mum CMOS process. By using a power splitter and a delay path in the feedback loop connecting the output and current source of the oscillator, a part of the oscillator output power injects to the oscillator itself. With the proper phase delay in the feedback loop and high transconductance of the current source, a low phase-noise oscillator is achieved. The amplitude stability and phase stability are analyzed, the phenomena of the phase-noise reductions are derived, and the device-size selections of the oscillator are investigated. The time-variant function, impulse sensitivity function, is also adopted to analyze the phase-noise reductions of the second-harmonic self-injected push-push oscillator. These theories are verified by the experiments. This self-injected push-push oscillator achieves low phase noise of -120.1 dBc/Hz at 1-MHz offset from the 9.6-GHz carrier. The power consumption is 13.8 mW from a 1.0-V supply voltage. The figure-of-merit of the oscillator is -188.3 dBc/Hz. It is also the first attempt to analyze the second-harmonic self-injected push-push oscillator     

一种三阶环形压控振荡器的分析设计

This paper describes a large tuning range low phase noise voltage-controlled ring oscillator(ring VCO)based on a different cascade voltage logic delay cell with current-source load to change the current of output node.The method for optimization is presented.Furthermore,the analysis of performance of the proposed ring VCO is confirmed by the measurement results.The three-stage proposed ring VCO was fabricated in the 180-nm CMOS process of SMIC.The measurement results show that the oscillator frequency of the ring VCO is from 0.770 to5.286 GHz and the phase noise is 97.93 dBc/Hz at an offset of 1 MHz from 5.268 GHz with a total power of15.1 mW from a 1.8 V supply while occupying only 0.00175 mm2of the core die area.     

Jitter and phase noise of ADPLL due to PSN with deterministic frequency

In this article, jitter and phase noise of all-digital phase-locked loop due to power supply noise (PSN) with deterministic frequency are analysed. It leads to the conclusion that jitter and phase noise heavily depend on the noise frequency. Compared with jitter, phase noise is much less affected by the deterministic PSN. Our method is utilised to study a CMOS ADPLL designed and simulated in SMIC 0.13?µm standard CMOS process. A comparison between the results obtained by our method and those obtained by simulation and measurement proves the accuracy of the predicted model. When the digital controlled oscillator was corrupted by PSN with 100?mVpk-pk, the measured jitters were 33.9?ps at the rate of f_G?=?192?MHz and 148.5?ps at the rate of f_G?=?40?MHz. However, the measured phase noise was exactly the same except for two impulses appearing at 192 and 40?MHz, respectively.     

A 67-GHz low-phase-noise oscillator and its application in a polar transmitter

In this paper, a low-phase-noise 67-GHz CMOS oscillator is presented. This inductorless voltage-controlled oscillator (VCO) employs a combination of standing-wave and travelling-wave oscillators to generate multi-phase outputs. A filtering technique is used to reduce the phase noise of the VCO. The oscillator achieves a tuning range of 5.2 GHz using a combination of coarse and fine tuning methods. The proposed multi-phase oscillator is designed and fabricated in a 0.13-μm CMOS process. Operating at 67 GHz, the VCO consumes 14 mW from a 1.2-V supply and achieves an output phase noise of −95.66 dBc/Hz (−107.89 dBc/Hz) at a 1 MHz (10 MHz) offset. The chip area is 0.9 mm². As an application example for the presented multi-phase oscillator, a polar transmitter structure is proposed. The transmitter is designed for systems that use a circular quadrature-amplitude modulation (QAM) constellation. A specific example of a 16-QAM transmitter is presented. The desired output phase is chosen by an 8-to-1 multiplexer, and a variable gain amplifier (VGA) is used to achieve the desired amplitude. Based on post-layout simulations, the 60-GHz 16-QAM transmitter consumes 43.2 mW from a 1.2-V supply.     

Cell-based fully integrated CMOS frequency synthesizers

A family of standard cells for phase-locked loop (PLL) applications is presented. The applications are processed using a 1.5 μm, n-well, double-polysilicon, double-layer metal CMOS process. Applications include frequency synthesis for computer clock generation, disk drives, and pixel clock generators for computer monitors, with maximum frequencies up to 80 MHz. The synthesizers require no external components since the loop filter and oscillator are on chip with the phase frequency detector and the charge pump. Special voltage and current reference cells are discussed. Analysis of noise sources in the PLL demonstrates the need for reducing the phase noise of the system. A low phase noise is achieved through supply rejection techniques and by placing the oscillator in a high-gain feedback loop to minimize its noise contributions. Laboratory measurements of completed silicon show synthesizers with exceptionally linear gain, as well as transient responses and phase noise similar to predicted results     

Design and Analysis of a 90 nm mm-Wave Oscillator Using Inductive-Division LC Tank

A 60 GHz voltage-controlled oscillator with an inductive division LC tank has been designed in 90 nm CMOS. The analysis of the oscillator shows that the presence of higher harmonics, the capacitance nonlinearity and the very high $K _{rm VCO}$ are critical for the phase noise performance of oscillators. Therefore, a pseudo-differential amplifier is employed in this design because of its high linearity. Furthermore, the proposed inductive division reduces the phase noise by increasing the signal amplitude across the varactor, without affecting the operation mode of the cross-coupled pair transistors. It also helps to increase the tuning range by isolating the varactor from the parasitic capacitances of the transistors and interconnects. The mm-wave oscillator is fabricated in a 90 nm CMOS technology. Under 0.7 V supply, the oscillator achieves a tuning range from 53.2 GHz to 58.4 GHz, consuming 8.1 mW. At 58.4 GHz, the phase noise is $-hbox{91~dBc}/hbox{Hz}$ at 1 MHz offset. Under 0.43 V supply, the oscillator achieves a tuning range from 58.8 to 61.7 GHz. At 61.7 GHz, the phase noise is $-hbox{90~dBc}/hbox{Hz}$ @1$~$MHz offset with a power consumption of only 1.2 mW.      

Silicon-based distributed voltage-controlled oscillators

Distributed voltage-controlled oscillators (DVCOs) are presented as a new approach to the design of silicon VCOs at microwave frequencies. In this paper, the operation of distributed oscillators is analyzed and the general oscillation condition is derived, resulting in analytical expressions for the frequency and amplitude. Two tuning techniques for DVCOs are demonstrated, namely, the inherent-varactor tuning and delay-balanced current-steering tuning. A complete analysis of the tuning techniques is presented. CMOS and bipolar DVCOs have been designed and fabricated in a 0.35-μm BiCMOS process. A 10-GHz CMOS DVCO achieves a tuning range of 12% (9.3-10.5 GHz) and a phase noise of -103 dBc/Hz at 600 kHz offset from the carrier. The oscillator provides an output power of -4.5 dBm without any buffering, drawing 14 mA of dc current from a 2.5-V power supply. A 12-GHz bipolar DVCO consuming 6 mA from a 2.5-V power supply is also demonstrated. It has a tuning range of 26% with a phase noise of -99 dBc/Hz at 600 kHz offset from the carrier     

Frequency Switching in Dual-Resonance Oscillators

An oscillator with a high-order (>2) resonator has multiple stable modes of oscillations. The stable modes for one such oscillator, having a fourth-order resonator, are found using a nonlinear analysis. By using a proper nonlinear active topology and tank component values, the fourth-order oscillator can generate either of the two distinct frequencies f₁ or f₂. A method is introduced to dynamically switch between the stable modes of oscillations. It is shown that the phase noise of this fourth-order oscillator, when generating only one of its resonant frequencies, is comparable to the phase noise of a second-order oscillator using the same active topology and resonator quality factor. Furthermore, the fourth-order oscillator has better phase noise and/or higher tuning range in VCO implementations compared to the commonly used switched resonator oscillators. The claims have been verified experimentally through an integrated oscillator prototype with f₁ = 2.4 GHz and f₂ = 4.7 GHz fabricated in a standard 0.18 mum CMOS technology. The oscillator draws 1.89 mA current of 1.8 V supply. The 1 MHz offset phase noises of the fourth-order oscillator for f₁ = 2.4 GHz and f₂ = 4.7 GHz are -122.4 dBc/Hz and -123.4 dBc/Hz, respectively     

A 5 GHz, 192.6 dBc/Hz/mW FOM, LC–VCO System With Amplitude Control Loop and LDO Voltage Regulator in 0.18 μm CMOS

To reduce phase noise degradation from oscillator tail current sources, this letter presents an inductor-capacitor voltage-controlled oscillator (LC-VCO) biased by triode metal-oxide-semiconductor transistors. The VCO system also includes an amplitude control loop and a voltage regulator to endure process, voltage, and temperature variations and to enhance power supply rejection ratio. Fabricated in a 0.18 mum CMOS process, the measured results show the adopted topology achieves a better phase noise than the conventional saturation current source. At 5.181 GHz, the VCO system demonstrates a phase noise of -104.8 dBc/Hz at 100-kHz offset, and -127.1 dBc/Hz at 1 MHz offset, while dissipating 4.2 mA from a 1.8 V supply voltage. The corresponding figures of merit at 100 kHz and 1 MHz offset are 190.3 and 192.6 dBc/Hz/mW, respectively.     

New implementation of injection locked technique and its application to low phase noise quadrature oscillators

A new implementation of the injection locked technique is proposed. The incident signal is directly injected into the common-source connection node of the sub-harmonic oscillator instead of the gate of the tail current source, and a narrowband noise filtering network is inserted into the same node to suppress the tail current source noise. A novel quadrature oscillator with the proposed injection locked technique is presented. The simulations show that the phase noise of the quadrature oscillator is about 7 dB better than that of the stand-alone sub-harmonic oscillator. The quadrature oscillator has been implemented in 0.25 um CMOS process and the measured results show that the proposed quadrature oscillator could achieve a phase noise of −130 dBc/Hz at 1 MHz offset from 1.13 GHz carrier while only drawing an 8.0 mA current from the 2.5 V power supply.     

基于802．11a标准的5GHz振荡器设计

介绍了一种全集成的LC压控振荡器（VCO）的设计。该振荡器的中心频率为5．25GHz,电源电压为1．8V,工作在802．11a标准下,采用0．18μmCMOS工艺实现。仿真结果表明。VCO的相位噪声在偏离中心频率1MHz时达到-121dBc／Hz,调谐范围达到31％,输出电压峰峰值为830mV,有良好的线性纯度。     

精确的1.08GHz CMOS电感电容压控振荡器

在0.35μm 2P4M标准CMOS工艺上,设计了一个精确的1.08GHz CMOS电感电容压控振荡器.提出了一种有效计算压控振荡器周期的新方法,采用该方法计算的频率-电压调谐曲线与实验结果吻合得很好.在电源电压3.3V下,消耗电流3.1mA,压控振荡器的相位噪声在10kHz频偏处为-82.2dBc/Hz.芯片面积为0.86mm×0.82mm.