Impact of high-/spl kappa/ dielectric HfO/sub 2/ on the mobility and device performance of sub-100-nm nMOSFETs

Scaling of Si MOSFETs beyond the 90-nm technology node requires performance boosters in order to satisfy the International Technology Roadmap for Semiconductors requirements for drive current in high-performance transistors. Amongst the preferred near term solutions are transport enhanced FETs utilizing strained Si (SSi) channels. Additionally, high-/spl kappa/ dielectrics are expected to replace SiO/sub 2/ around or after the 45-nm node to reduce the gate leakage current problem, facilitating further scaling. However, aside from the many technological issues such as trapped charge and partial crystallization of the dielectric, both of which are major issues limiting the reliability and device performance of devices employing high-/spl kappa/ gate stacks, a fundamental drawback of MOSFETs with high-/spl kappa/ dielectrics is the mobility degradation due to strong soft optical phonon scattering. In this work we study the impact of soft optical phonon scattering on the mobility and device performance of conventional and strained Si n-MOSFETs with high-/spl kappa/ dielectrics using a self-consistent Poisson Ensemble Monte Carlo device simulator, with effective gate lengths of 67 and 25-nm. Additionally we have also briefly investigated the effect (the percentage change) that a trapped charge within the gate oxide will have on the drive current for both a SiO/sub 2/ oxide and an equivalent oxide thickness of high-/spl kappa/ dielectric.     

SEU reliability analysis of advanced deep-submicron transistors

A systematic evaluation of the single-event-upset (SEU) reliability of the advanced technologies-high-/spl kappa/ gate dielectric, elevated source-drain (E-SD), and lateral asymmetric channel (LAC) MOSFETs is presented for the first time in this work. Our simulations results gives a clear view of how the short channel effects in a device governs its SEU reliability and how this reasoning evolves at the circuit level. It is shown that devices with worsened short-channel effects (high-/spl kappa/ gate dielectric transistors) have a significantly reduced SEU-reliability in contrast to the devices with controlled short-channel effects (LAC and E-SD) or even a conventional device.     

Special reliability features for Hf-based high-/spl kappa/ gate dielectrics

Several special reliability features for Hf-based high-/spl kappa/ gate dielectrics are highlighted, including: 1) trapping-induced threshold voltage (V/sub th/) shift is much more of a concern than TDDB in determining the operating lifetime; 2) n-channel MOSFETs (nMOSFETs) are more vulnerable than p-channel MOSFETs (pMOSFETs); and 3) MOSFETs with polySi gates are more vulnerable than those with metal gates. These will be discussed in the context of existing electron/hole traps and trap generation by high-field stress. A novel technique to probe traps in ultrathin gate dielectrics, inelastic electron tunneling spectroscopy (IETS), will be shown to be capable of revealing the energies and locations of traps in high-/spl kappa/ gate dielectrics.     

Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks

Over recent years, there has been increasing research and development efforts to replace SiO/sub 2/ with high dielectric constant (high-/spl kappa/) materials such as HfO/sub 2/, HfSiO, and Al/sub 2/O/sub 3/. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-/spl kappa/ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.     

Measurement of the interface trap and dielectric charge density in high-/spl kappa/ gate stacks

We demonstrate an accurate measurement of the interface trap density and the stress-induced dielectric charge density in Si/high-/spl kappa/ gate dielectric stacks of metal-oxide-semiconductor field-effect transistors (MOSFETs) using the direct-current current-voltage (DCIV) technique. The capture cross section and density of the interface traps in the high-/spl kappa/ gate stack were found to be similar to those of the Si/SiO/sub 2/ interface. A constant-voltage stress of the p-channel MOSFET in inversion is shown to result in a negative dielectric charging and an increase in the interface trap density.     

Hot carrier degradation of HfSiON gate dielectrics with TiN electrode

Hot carrier reliability of the HfSiON dielectric with the TiN metal gate electrode has been studied in the nMOS and pMOS short channel transistors. Hot carrier induced degradation of the high-/spl kappa/ gate stack devices are severe than the one in the SiO/sub 2//poly devices. It is determined that total threshold voltage shift during a hot carrier stress is a sum of contributions from both hot carrier and cold carrier effects. The hot carrier contribution induces permanent damage while cold carrier contribution is shown to be reversible. The contribution from the cold carrier can be evaluated by applying a de-trapping (opposite polarity) bias after the stress.     

Electron trap generation in high-/spl kappa/ gate stacks by constant voltage stress

Positive bias constant voltage stress combined with charge pumping (CP) measurements were applied to study trap generation phenomena in SiO/sub 2//HfO/sub 2//TiN stacks. Using gate stacks with varying thicknesses of the interfacial SiO/sub 2/ layer (IL) or high-/spl kappa/ layer and analysis for frequency-dependent CP data developed to address trap depth profiling, the authors have determined that the defect generation in the stress voltage range of practical importance occurs primarily within the IL on as-grown "precursor" defects most likely caused by the overlaying HfO/sub 2/ layer. The generated traps can be passivated by a forming gas or nitrogen (N/sub 2/) anneal, whereas a postanneal stress reactivates these defects. The results obtained identify the IL as one of the major targets for reliability improvement of high-/spl kappa/ stacks.     

Magnetic resonance studies of trapping centers in high-/spl kappa/ dielectric films on silicon

The electrical properties of high dielectric constant materials being considered for replacements of SiO/sub 2/ in metal-oxide semiconductor (MOS) field effect transistors are dominated by point defects. These point defects play important roles in determining the response of these films in almost any imaginable reliability problem. A fundamental understanding of these defects may help to alleviate the problems which they can cause. The best known methods for determining the structure of electrically active defects in MOS materials and devices are conventional electron spin resonance (ESR) and electrically detected magnetic resonance (EDMR). In this paper, we review the limited ESR and EDMR work performed to date on high-/spl kappa/ materials. A discussion of magnetic resonance techniques as well as a brief overview of the extensively studied Si/SiO/sub 2/ system is also included.     

The statistics of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in pMOSFETs

Negative bias temperature instability (NBTI) is a pFET degradation mechanism that can result in threshold voltage shifts up to 100 mV or more, even in very thin oxide devices. Since analog circuits that utilize matched pairs of devices, such as current mirrors and differential pairs, generally depend on V/sub T/ matching considerably better than this, NBTI-induced V/sub T/ mismatch shift may represent a serious reliability concern for CMOS analog applications. Furthermore, induced /spl beta/ mismatch shift (affecting drain current level at a fixed gate overdrive voltage) may also impact drain current and transconductance mismatch. In this paper, experimental results of the statistics and scaling properties of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in saturation, and models describing these results, are presented.     

Conduction band-edge States associated with the removal of d-state degeneracies by the Jahn-Teller effect

X-ray absorption spectroscopy (XAS) is used to study band edge electronic structure of high-/spl kappa/ transition metal (TM) and trivalent lanthanide rare earth (RE) oxide gate dielectrics. The lowest conduction band d/sup */-states in TiO/sub 2/, ZrO/sub 2/ and HfO/sub 2/ are correlated with: 1) features in the O K/sub 1/ edge, and 2) transitions from occupied Ti 2p, Zr 3p and Hf 4p states to empty Ti 3d-, Zr 4d-, and Hf 5d-states, respectively. The relative energies of d-state features indicate that the respective optical bandgaps, E/sub opt/ (or equivalently, E/sub g/), and conduction band offset energy with respect to Si, E/sub B/, scale monotonically with the d-state energies of the TM/RE atoms. The multiplicity of d-state features in the Ti L/sub 2,3/ spectrum of TiO/sub 2/, and in the derivative of the O K/sub 1/ spectra for ZrO/sub 2/ and HfO/sub 2/ indicate a removal of d-state degeneracies that results from a static Jahn-Teller effect in these nanocrystalline thin film oxides. Similar removals of d-state degeneracies are demonstrated for complex TM/RE oxides including Zr and Hf titanates, and La, Gd and Dy scandates. Analysis of XAS and band edge spectra indicate an additional band edge state that is assigned Jahn-Teller distortions at internal grain boundaries. These band edges defect states are electronically active in photoconductivity (PC), internal photoemission (IPE), and act as bulk traps in metal oxide semiconductor (MOS) devices, contributing to asymmetries in tunneling and Frenkel-Poole transport that have important consequences for performance and reliability in advanced Si devices.     

Wafer level reliability and lifetime analysis of InGaAsP/InP quantum-well Fabry-Perot laser diode

This paper investigated the reliability of semiconductor 1.3-/spl mu/m multiquantum-well (MQW) Fabry-Perot laser diodes (LDs) in a quarter 2-in wafer level that are measured to have uniform threshold currents, slope efficiencies, and wavelengths within 4% of the maximum deviation. By performing the accelerated aging test under a constant optical power of 3 mW at 85/spl deg/C for 2100 h, the lifetime of the fabricated optoelectronic devices was estimated, where the failure rate was matched on the fitted line of the lognormal distribution model resulting in the mean-time-to-failure (MTTF) of 2/spl times/10/sup 6/ h operating at room temperature.     

MOS Technology Drivers

The semiconductor industry has entered a new revolution where connectivity, applications, and an overall pervasive market drives the need for increased circuit density, improved performance, and a decrease in power dissipation. These issues are the backbone for some of the latest silicon technology advancements, including the integration of stress-enabled transistors and advanced silicon-on-insulator substrates. Future advancements may include multiple gated devices, high- gate oxides, and band-gap-tailored devices. This paper will review some of the early complementary metal-oxide-semiconductor transistor reliability issues and solutions that have allowed this industry to flourish over the last 25 years. A discussion on how these past issues and new advances affect power versus performance is the framework and motivation of this paper.     

ESD failure mechanisms of analog I/O cells in 0.18-/spl mu/m CMOS technology

Different electrostatic discharge (ESD) protection schemes have been investigated to find the optimal ESD protection design for an analog input/output (I/O) buffer in 0.18-/spl mu/m 1.8- and 3.3-V CMOS technology. Three power-rail ESD clamp devices were used in power-rail ESD clamp circuits to compare the protection efficiency in analog I/O applications, namely: 1) gate-driven NMOS; 2) substrate-triggered field-oxide device, and 3) substrate-triggered NMOS with dummy gate. From the experimental results, the pure-diode ESD protection devices and the power-rail ESD clamp circuit with gate-driven NMOS are the suitable designs for the analog I/O buffer in the 0.18-/spl mu/m CMOS process. Each ESD failure mechanism was inspected by scanning electron microscopy photograph in all the analog I/O pins. An unexpected failure mechanism was found in the analog I/O pins with pure-diode ESD protection design under ND-mode ESD stress. The parasitic n-p-n bipolar transistor between the ESD clamp device and the guard ring structure was triggered to discharge the ESD current and cause damage under ND-mode ESD stress.     

BTI characteristics and mechanisms of metal gated HfO/sub 2/ films with enhanced interface/bulk process treatments

Significant deviations in BTI characteristics for metal gate HfO/sub 2/ films compared to silicon oxide based films prove that conventional reliability models based on SiO/sub 2/ films can no longer be directly applied to HfO/sub 2/ based MOSFETS. This study shows the use of conventional accelerated reliability testing in the Fowler-Nordheim tunneling regime to extrapolate time to failure at operating voltages (direct tunneling regime) overestimates device lifetimes. Additionally, unlike conventional gate oxides, the slope of /spl Delta/V/sub t/ versus time (or the rate of charge trapping) in HfO/sub 2/ MOSFETS is dependent on stress voltage. The HfO/sub 2/ based metal gated nMOSFETS show poor PBTI characteristics and do not meet the 10 year lifetime criterion for threshold voltage stability. On the other hand, HfO/sub 2/ based pMOSFETS show superior NBTI behavior and meet the 10 year lifetime criterion. These results are contrary to the observations with conventional gate dielectrics. This paper explores the anomalous charge trapping behavior and provides a comprehensive study of the PBTI characteristics and recovery mechanisms in metal gated HfO/sub 2/ films.     

Effect of metal contaminants in pre-gate oxide cleans for sub-100-nm devices

Metal contaminants at trace levels in the pre-gate oxide clean solutions have always been a concern with scaling down trends in CMOS-based devices. The effect of multielement contamination (alkali, transition, and noble metals up to 200 ppb levels) in dilute hydrofluoric acid (DHF), standard clean one (SC1), and standard clean two (SC2) solutions is investigated for an Intel Pentium-based sub-100-nm microprocessor technology. The main significance of this work is to achieve a rational specification for process chemical purity. Results from surface analyses of monitor wafers and device level electrical measurements of production scale wafers along with yield and reliability analyses are presented in this paper. Deposition of metallic contaminants from clean solutions has been explained qualitatively based on electrochemical theory of reduction potentials. Among the 35 elements investigated in this study, only platinum at very low parts-per-billion levels in the HF-based cleans has been found to affect the gate oxide integrity producing zero yield. An increase in the surface roughness (2-8/spl times/) was also observed with silicon monitor wafers for 100-ppb-platinum-contaminated DHF solutions and could play an important role in degrading the gate oxide performance. Other alkali and transition metals including copper up to 200 ppb levels in the HF-based cleans studied here did not show any deleterious effects in the gate oxide integrity and product reliability measurements. The effect of contamination in the SC1 and SC2 cleans was negligible even for 100 ppb platinum. Significant cost reduction can be realized by safely relaxing the process chemical contamination disposition limits for alkali and transition elements.     

Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits

As the technology feature size is reduced, the thermal management of high-performance very large scale integrations (VLSIs) becomes an important design issue. The self-heating effect and nonuniform power distribution in VLSIs lead to performance and long-term reliability degradation. In this paper, we analyze the self-heating effect in high-performance sub-0.18-/spl mu/m bulk and silicon-on-insulator (SOI) CMOS circuits using fast transient quasi-dc thermal simulations. The impact of the self-heating effect and technology scaling on the metallization lifetime and the gate oxide time-to-breakdown (TBD) reduction are also investigated. Based on simulation results, an optimized clock-driver design is proposed. The proposed layout reduces the hot-spot temperature by 15/spl deg/C and by 7/spl deg/C in 0.09-/spl mu/m SOI and bulk CMOS technologies, respectively.     

Crosstalk overshoot/undershoot analysis and its impact on gate oxide reliability in multi-wall carbon nanotube interconnects

The work in this paper analyzes the crosstalk effects in Multi-wall Carbon Nanotube (MWCNT) based interconnect systems, and its impact on the reliability of the gate oxide of MOS devices. The electrical circuit parameters for interconnect are calculated using the existing models of MWCNT and the equivalent circuit has been developed to perform the crosstalk analysis. The crosstalk induced overshoot/undershoots have been estimated and the effect of the overshoot/undershoots on the gate oxide reliability is calculated in terms of failure-in-time (FIT) rate of the MOS devices. Single, double, and bundle of MWCNTs are considered for the analysis. The results are compared with that of traditional Cu based interconnects. It has been found that the average failure rate due to crosstalk overshoot/undershoots is ??10 to 100 times less in MWCNT based interconnect of length between 10 ??m to 50 ??m as compared to the copper based interconnects. Our analysis shows the applicability of MWCNTs in future VLSI circuits from the perspective of gate oxide reliability. The results also reveal that single or double MWCNT of large diameter is better than bundle of MWCNTs of smaller diameter.     

Quantum Simulation Study of a New Carbon Nanotube Field-Effect Transistor With Electrically Induced Source/Drain Extension

In this paper, we present the unique features exhibited by a proposed structure of coaxially gated carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions using the self-consistent and atomistic scale simulations, within the nonequilibrium Green's function formalism. In this novel CNTFET structure, three adjacent metal cylindrical gates are used, where two side metal gates with lower workfunction than the main gate as an extension of the source/drain on either side of the main metal gate are biased, independent of the main gate, to create virtual extensions to the source and the drain and also to provide an effective electrical screen for the channel region from the drain voltage variations. We demonstrate that the proposed structure of CNTFET shows improvement in device performance focusing on leakage current, on–off current ratio, and voltage gain. In addition, the investigation of short-channel effects for the proposed structure shows improved drain-induced barrier lowering, hot-carrier effect, and subthreshold swing, all of which can affect the reliability of CMOS devices.      

Enhanced SiO/sub 2/ reliability on deuterium-implanted silicon

Stress-induced leakage current and time-dependent dielectric breakdown were investigated to examine the reliability of gate oxides grown on hydrogen- and deuterium-implanted silicon substrates. An order of magnitude improvement in charge-to-breakdown was observed for the deuterium-implanted devices as compared with the hydrogen-implanted ones. Such reliability improvement may be explained by the reduction of defects in the SiO/sub 2/ and Si/SiO/sub 2/ interface, such as Si dangling bonds, weak Si-Si bonds, and strained Si-O bonds due to the retention of implanted deuterium at the interface and in the bulk oxide as confirmed by secondary ion mass spectroscopy.     

高压大功率器件用高温栅偏测试装置研制

为准确评估硅IGBT和碳化硅MOSFET等高压大功率器件不同电应力及热应力条件下的栅极可靠性,研制了实时测量皮安级栅极漏电流的高温栅偏（high temperature gate bias,HTGB）测试装置。此外,该测试装置具备阈值电压在线监测功能,可以更好地监测被测器件的状态以进行可靠性评估和失效分析。为初步验证测试装置的各项功能和可靠性,运用该测试装置对商用IGBT器件在相同温度应力不同电应力条件下进行分组测试。初步测试结果表明老化初期漏电流逐渐降低,最终漏电流大小与电压应力有良好的正相关性,栅偏电压越大,漏电流越大。该测试装置实现了碳化硅MOSFET器件和硅IGBT器件对高温栅偏的测试需求且适用于各种类型的封装。