TFT-LCD过孔接触电阻研究

研究了过孔接触电阻变化规律,并进行机理分析,为优化薄膜晶体管的过孔设计提供依据。首先,运用开尔文四线检测法对不同大小、形状、数量的钼/铝/钼结构的栅极和源/漏层金属与氧化铟锡连接过孔的接触电阻进行测试。然后,通过扫描电子显微镜、能量色散X射线光谱仪和聚焦离子束显微镜对过孔内部形貌进行表征。最后,对过孔接触电阻变化规律进行机理分析。实验结果表明:过孔面积越大,接触电阻越小;过孔面积相同时,长方形过孔的接触电阻小于正方形过孔的接触电阻,多小孔的接触电阻小于单大孔的接触电阻,栅极金属与氧化铟锡的过孔接触电阻小于源/漏层金属与氧化铟锡的过孔接触电阻。为了降低钼/铝/钼与氧化铟锡连接过孔的接触电阻,过孔面积尽可能最大化,采用长方形过孔优于正方形过孔,多小过孔优于单大孔设计,同时优化过孔刻蚀工艺,减少过孔内顶层钼的损失。     

Influence of short circuits on data of contact and via opencircuits determined by a novel weave test structure

Generally test structures containing via strings and contact strings are used to control backend isolation layers' integrity. However, short circuits are the major type of fault resulting from defects during the backend process steps. For this reason, the influence that short circuits have on contact hole open circuits and via hole open circuits in regular string test structures will be investigated here. A novel weave test structure (WTS) is presented to detect open circuits as well as short circuits in adjacent conducting layers of backend process steps. Numerous contact strings or via strings are arranged inside boundary pads like a woven piece of cloth. Thus, short circuits between different strings are also electrically detectable. The separation and localization of defects will be achieved by dividing the chip area into distinguishable subchips inside given standard boundary pads without using any active semiconductor devices. The localization enables a versatile optical defect parameter extraction to precisely determine the reason why and how a defect occurred during the manufacturing process     

Some methods for defining design rules

Some new methods to define design rules for integrated-circuits by evaluating a large quantity of results measured from test structures are described. To define the minimum area of a contact hole, more detailed methods are discussed than simple yield analysis: for example, the analysis of the resistances measured or of the local distribution of defects. Using a special test structure of misaligned contact holes, important data for the design rules, such as the alignment tolerance and the mask tolerance, can be defined experimentally.     

Electrical linewidth test structures fabricated in monocrystallinefilms for reference-material applications

The physical widths of reference features incorporated into electrical linewidth test structures patterned in films of monocrystalline silicon have been determined from Kelvin voltage measurements. The films in which the test structures are patterned are electrically insulated from the bulk-silicon substrate by a layer of silicon dioxide provided by SIMOX (Separation by the IMplantation of OXygen) processing. The motivation is to facilitate the development of linewidth reference materials for critical-dimension (CD) metrology-instrument calibration. The selection of the (110) orientation of the starting silicon and the orientation of the structures' features relative to the crystal lattice enable a lattice-plane-selective etch to generate reference-feature properties of rectangular cross section and atomically planar sidewalls. These properties are highly desirable for CD applications in which feature widths are certified with nanometer-level uncertainty for use by a diverse range of CD instruments. End applications include the development and calibration of new generations of CD instruments directed at controlling processes for manufacturing devices having sub-quarter-micrometer features     

Encapsulating Elastically Stretchable Neural Interfaces: Yield,Resolution, and Recording/Stimulation of Neural Activity

A high‐resolution elastically stretchable microelectrode array (SMEA) for interfacing with neural tissue is described. The SMEA consists of an elastomeric substrate, such as poly(dimethylsiloxane) (PDMS), elastically stretchable gold conductors, and an electrically insulating encapsulating layer in which contact holes are opened. We demonstrate the feasibility of producing contact holes with 40 μm × 40 μm openings, show why the adhesion of the encapsulation layer to the substrate is weakened during contact hole fabrication, and provide remedies. These improvements result in greatly increased fabrication yield and reproducibility. An SMEA with 28 microelectrodes was fabricated. The contact holes (100 μm × 100 μm) in the encapsulation layer are only ～10% the size of the previous generation, allowing a larger number of microelectrodes per unit area, thus affording the capability to interface with a smaller neural population per electrode. This new SMEA is used to record spontaneous and evoked activity in organotypic hippocampal tissue slices at 0% strain before stretching, at 5% and 10% equibiaxial strain, and again at 0% strain after relaxation. Stimulus–response curves at each strain level are measured. The SMEA shows excellent biocompatibility for at least two weeks.     

The HARPSS process for fabrication of precision MEMS inertial sensors

The high aspect-ratio combined poly- and single-crystal silicon micromachining technology (HARPSS) and its application to fabrication of precision MEMS inertial sensors are presented. HARPSS is a single wafer, all silicon, front-side release process which is capable of producing 10–100's of microns thick, electrically isolated, 3-D poly- and single-crystalline silicon microstructures with various size air-gaps ranging from sub-micron to tens of microns. High aspect-ratio (>50:1) polysilicon structures are created by refilling 100's of microns deep trenches with polysilicon deposited over a sacrificial oxide layer. This technology provides features required for precision micromachined inertial sensors. The all-silicon feature of this technology improves long term stability and temperature sensitivity while fabrication of large area, vertical electrodes with sub-micron gap spacing will increase the sensitivity by orders of magnitude.     

晶体硅片上激光打孔的研究

背面接触太阳电池越来越多地被人们关注,这种电池增加了使用激光器在硅片上打孔工艺。选用了半导体激光器作为光源在晶体硅片上进行打孔实验。通过调节激光器的功率、离焦量、脉冲重复频率等参数并分析其对打孔的影响。在激光打孔后,对硅片使用显微镜测试来分析打孔大小、形貌和损伤区,并优化打孔的参数。通过实验证实孔的入孔直径和出孔直径都随激光能量的增大而增大。随着离焦量的增大,出孔直径先增大后减小,且出孔直径越大时孔附近的破坏区域越小。脉冲重复频率的变化由于影响激光能量而影响孔径。另外,脉冲重复频率过大时,激光能量仍然比较大,但却打不穿硅片。     

一种提高波纹管型自调式J-T制冷器控温精度的设计及试验研究

为提高波纹管型J-T制冷器的控温精度,对阀针进行了优化设计.在阀针针尖部位开槽,使其与制冷器阀体上的主节流孔形成双节流孔.制冷器开启后,工质进入主节流孔,节流降温;制冷器自调后,阀针完全堵住主节流孔,稳定小流量从针槽喷出.通过试验确定了阀针开槽的合理尺寸范围.试验结果表明,阀针开槽可以有效提高制冷器的控温精度.     

飞秒激光制备阵列孔金属微滤膜

选用不锈钢、铜和铝三种金属薄膜作为实验材料,厚度10~50μm.对不锈钢、铜和铝三种金属薄膜进行飞秒激光加工,研究了所形成的微纳米孔直径与飞秒激光加工参数的关系.结果表明,飞秒激光加工的微孔直径随单脉冲能量和脉冲数的平方根的增大而增大.不锈钢薄膜适于飞秒激光制作金属微孔膜,在25μm厚的不锈钢薄膜上制备了大面积阵列微孔,孔直径为2.5~10μm,孔间距为10~50μm.与传统烧结金属微孔过滤膜比较,飞秒激光制备阵列微孔金属膜具有膜孔尺寸均匀一致、直通孔形、膜孔尺寸和间距可控等特点,可获得较高的孔隙率,有利于提高透过水通量.     

A methodology to extract failure rates for low-k dielectric breakdown with multiple geometries and in the presence of die-to-die linewidth variation

Backend geometries on chips contain a wide variety of features. This paper analyzes data from test structures implemented on a 45 nm technology test chip to relate geometry to failure rate statistics. An area scaling model is constructed which accounts for the presence of die-to-die linewidth variation, and a methodology is proposed to account for die-to-die linewidth variation when determining if low-k materials satisfy lifetime requirements.     

Characterization of 23-percent efficient silicon solar cells

A silicon solar cell structure, PERC (passivated emitter and rear cell), has very recently demonstrated energy conversion efficiency above 23%. A number of interesting features of the PERC cell design are discussed. Rear contact design is based on a balance between the beneficial effects of small sparsely spaced contact points upon the open circuit voltage and short-circuit current of the cell and the corresponding negative effects upon cell fill factor. The noncontacted regions of the rear surface are held in weak depletion by an optically isolated but electrically connected rear Al reflector. Once bulk injection levels become appreciable, the disadvantage of this surface condition disappears. The structure incorporates a reasonably effective light-trapping scheme, although there remains scope for improvements in this area. Along with other improvements, efficiency approaching 24% seems feasible with the present cell structure. If a processing regime can be found which allows boron passivation of the contact holes or the entire rear surface without loss of the present exceptionally high bulk lifetimes, efficiencies above 24% are likely     

适合于改善金属接触孔清洗的单晶圆工艺

在半导体制造流程中,晶圆清洗正在成为一种更加关键的工序模块。因为集成度的提高,需制定适合于清洗机及更高器件结构均匀性的要求。清洗的有效性最终会影响器件的性能和成品率[1-4]。无论在生产线前端或后端清洗工艺中,正在受到越来越仔细检查。在金属化工艺之前,一个有意义的方面是刻蚀和灰化后期金属接触孔侧壁和底部残留物的清除。因其会导致器件失效,一种不完全接触孔清洗技术成为一种主要的业务。     

The split-cross-bridge resistor for measuring the sheet resistance, linewidth, and line spacing of conducting layers

A new test structure was developed for evaluating the line spacing between conductors on the same layer by using an electrical measurement technique. This compact structure can also be used to measure the sheet resistance, linewidth, and line pitch of the conducting layer. Using an integrated-circuit fabrication process, this structure was fabricated in diffused polycrystalline silicon and metal layers. These structures were measured optically and electrically, and these measured value were compared. For the techniques used, the optical measurements were typically one-quarter micrometer greater than the electrical measurements for the polysilicon and metal layers. Most electrically measured line pitch values were within 2 percent of the designed value. A small difference between the measured and designed line pitch is used to validate sheet resistance, linewidth, and line spacing values. Test results confirm the structure's self-checking feature based on the line pitch. That is, a small difference between the measured and designed line pitch is used to validate sheet resistance, linewidth, and line spacing values. Rules for designing the test structure are presented in detail.     

Detouring dynamic routing holes in stationary wireless sensor networks in the presence of temporarily misbehaving nodes

In this work, we propose a scheme, named BRIDGE , to bypass dynamic routing holes arising in stationary wireless sensor networks in the presence of temporarily misbehaving nodes such as dumb 1 , 2 or transfaulty nodes. The affected nodes behave normally after the resumption of favorable environmental conditions. Therefore, both dumb and transfaulty behaviors of sensor nodes are dynamic in nature. The nodes in these networks get temporarily isolated from the network, when they behave as dumb or transfaulty. Because of the presence of nodes with such behavior, dynamic communication holes may occur in the network, which are formed or removed and thus increase or decrease in size with time. Connectivity re‐establishment procedures can mitigate holes by re‐connecting isolated nodes with the network after activating the intermediate sleep nodes, adjusting the communication range of intermediate nodes, or by using an alternative communication mode. However, such procedures cannot always re‐establish connectivity because of the lack of neighbor nodes in reduced or adjusted communication range. Therefore, routing schemes using greedy forwarding approaches need to bypass holes to avoid the data packets from getting stuck at the boundary nodes and efficiently delivering them to the sink. However, the existing hole avoidance schemes consider holes as static. The proposed scheme, BRIDGE , detects hole boundary and bypasses routing traffics in the dynamic hole scenario. In the proposed scheme, a boundary node selects the next hop based on the minimum distance from all the neighbor nodes to the destination node, although this minimum distance is more than the distance to the destination from the node itself. Simulation results show that the performance of the proposed scheme degrades with the increase in hole area. Copyright © 2015 John Wiley & Sons, Ltd.     

Impact of irregular geometries on low-k dielectric breakdown

Backend geometries on chips contain a wide variety of features. We are developing a full-chip reliability simulator for low-k dielectric breakdown that takes into account the vulnerable area, linewidth, vias, and line edge roughness. The simulator provides a link between test structure results and predictions of chip dielectric lifetime. However, these factors may not be sufficient for large chips with a wider variety of features. In this paper, we analyze data from backend dielectric test structures with irregular geometries to determine if more layout features need to be added to a full-chip reliability simulator for low-k dielectric breakdown.     

Mutual coupling in a finite planar array with interelement holespresent

The mutual coupling in a finite planar array with interelement holes present was considered. A computer program designed to study mutual coupling between rectangular waveguides was modified to include coupling between elements of different sizes. This modified program was used to study the problem of widely spaced rectangular waveguides that form smaller rectangular holes in the ground plane. Comparisons with experimental data confirmed the validity of the model. Tests run at various hole sizes showed that holes that are much smaller than their cutoff size have little effect on the coupling. For the rectangular-hole case, hole widths of less than half the cutoff width of the dominant mode had little effect     

基于双缝干涉水导激光打孔的仿真研究

水导激光加工技术具有热效应小、精度高、无刀具损坏等优点,被应用到高精度元件的加工中。为减小激光聚焦光斑直径以利于激光与水射流的精确耦合、提高激光孔的质量,提出了基于双缝干涉原理以减小激光聚焦光斑直径的方法。构建了传统水导激光和双缝干涉水导激光打孔的几何模型和数学模型;基于COMSOL分别进行仿真,对比和分析了在激光束参数、加工条件均相同的条件下,传统水导激光和双缝干涉水导激光打孔时对激光孔轮廓的演化、热影响区域分布和重铸层大小的影响。结果表明:与传统水导激光相比,采用双缝干涉水导激光加工技术能有效地减小激光孔直径、锥角、热影响区域宽度和重铸层大小,在现有条件下进一步减小激光聚焦光斑直径。     

柚子型光子晶体光纤布拉格光栅理论及实验研究

利用有限元法对一种柚子型光子晶体光纤中的传输模式进行了模拟,得到了各传输模式的有效折射率和模场分布。结合耦合模理论和相关函数方法,对柚子型光子晶体光纤布拉格光栅反射谱进行了理论分析,解释了柚子型光纤光栅出现多个谐振峰的原因;数值分析了光纤纤芯直径和空气孔尺寸对光栅传输谱的影响。结果表明谐振峰波长随纤芯直径的增大向长波方向漂移,而随空气孔增大向短波方向移动,并且不同谐振模式的变化幅度不同;利用相位模板法写制了光子晶体光纤光栅,实验结果与理论分析能够很好地吻合。     

Experimental verification of a novel electrical test structure formeasuring contact size

An electrical test structure that measures contact size without reliance on contact resistivity measurements is presented. A comparison with SEM photographs shows that the structure measures contact size in the range of 1.0 μm with a resolution close to 0.2 μm. Results are shown for measuring the size of contacts to poly, but the concept should also apply to measuring contacts to active areas, or contacts between two metal layers. In addition to the size of contacts to poly, the structure presented also measures the linewidth and sheet resistance of the poly, and misalignment of contacts to poly. It consists of a digital vernier of 72 samples and a linewidth structure and is implemented without active circuitry in a 2 by 12 pad array using three masking levels     

A new fabrication process of field emitter arrays with submicrongate apertures using local oxidation of silicon

The field emitter arrays with submicron gate apertures for low voltage operation have been successfully fabricated by modifying the conventional Spindt process. The key element of the new process is forming the gate insulator by local oxidation of silicon, resulting in the reduction of the gate hole size due to the lateral encroachment of oxide. The gate hole diameter of 0.55 μm has been obtained from the original mask pattern size of 1.55 μm. An anode current of 0.1 μA per emitter is measured at the gate voltage of about 53 V, while the gate current is less than 0.3% of the anode current. To obtain the same current level from a Spindt-type emitter with the same gate hole diameter as the mask pattern size, a gate bias of about 82 V is needed