用户可重构系统芯片-U-SoC

随着深亚微米技术(DSM)的不断发展,完全专用的系统芯片(SoC)已经面临新的问题和挑战.本文在研究硅技术发展趋势、硅产品特征循环规律以及硅产业结构演变规律的基础上,提出了一种具有一定“通用“性的用户可重构系统芯片(UserreconfigurableSoC,简称U-SoC),它通过用户重构功能降低新产品的开发成本,缩短上市周期,提高设计效率,从而增强了SoC的适应性和灵活性.研究U-SoC设计方法,对于加速我国微电子产业的发展进程,实现跨越式发展有重要作用.     

用户可重构系统芯片-U-SoC

随着深亚微米技术(DSM)的不断发展,完全专用的系统芯片(SoC)已经面临新的问题和挑战.本文在研究硅技术发展趋势、硅产品特征循环规律以及硅产业结构演变规律的基础上,提出了一种具有一定"通用"性的用户可重构系统芯片(UserreconfigurableSoC,简称U-SoC),它通过用户重构功能降低新产品的开发成本,缩短上市周期,提高设计效率,从而增强了SoC的适应性和灵活性.研究U-SoC设计方法,对于加速我国微电子产业的发展进程,实现跨越式发展有重要作用.     

可重构RF芯片相继问世

目前，以半导体厂家为中心，各个公司都在积极开发用一个芯片处理多个无线服务的多频带RF收发芯片。其目的在于通过将RF收发芯片与支持多协议的基带处理芯片集成在一起，开发出可利用手机网、WLAN室外热点，WiMAX等宽带无线服务、广播服务的终端。现在，美国的无线设计企业及大型半导体厂家正在开发可以收发4-5种无线频率、或可以自由转换收发频率的具有高附加值的多频带RF收发芯片。     

动态可重构技术打造更灵活的芯片

动态可重构是一种能够动态切换芯片电路结构的技术，目前，该技术正被越来越多地应用于各种设备中。例如，在复合机（MFP，Multi Function Peripheral）市场上，IPFlex公司是动态可重构技术的开创者，     

可重构模拟集成电路

本文介绍一种新型可重构模拟集成电路的结构，工作原理和使用方法。     

用户可重构系统芯片—U—SoC

随着深亚微米技术（DSM）的不断发展，完全专用的系统芯片（SOC）已经面临新问题和挑战。本文在研究硅技术发展趋势，硅产品特征循环规律以及硅产业结构演变规律的基础上，提出了一种具有一定“通用”性的用户可重构系统芯片（User reconfigurable Soc,简称U-SoC)，它通过用户重构功能降低新产品的开发成本，缩短上市周期，提高设计效率，从而增强了SoC的适应性和灵活性。研究U-Soc设计方法，对于加速我国微电子产业的发展进程，实现跨越式发展有重要作用。     

十亿晶体管级芯片系统集成面临的挑战与机遇

概述了半导体工业的发展趋势，讨论了10亿晶体管级芯片系统所面临的挑战，并提出了若干研究课题以获得即将来临的纳米时代的发展机遇。     

提高1Chip自动版图设计集成度的方法探讨

版图设计是IC设计中非常关键的一步。为了降低产品的成本，就需要在版图设计中提高设计的集成度，从而减小芯片的面积。而要做到这一点，除了更好地运用自动工具外，更重要的是发挥设计者的智慧才能，宏观上作好1ayout设计的“前奏”——1ayout布局，微观上考虑如何更充分地利用每一寸空间。本文就如何提高lChip版图设计的集成度进行了探讨。     

互联网在线可"重构"技术

当前的半导体工艺水平已经达到了深亚微米,正在向0.1μm以下发展.芯片的集成度达到1亿门,时钟频率也在向GHz以上发展.因此,未来的微电子技术的发展趋势,是把整个系统集成到一个芯片上去,这种芯片被称为系统芯片(System-on-a-chip).系统芯片比起当今的超大规模集成电路(VLSI)来说,无论是从集成规模和运行频率来说,都有极大的改进.     

博通推出业界集成度最高的Wi—Fi路由器芯片

新的Wi-Fi解决方案在可比较的价格点上比同类路由器性能高4倍,并利用Accelerange技术将覆盖范围提升1倍.     

Reconfigurable receiver approach for future wireless terminals

An overview on RF-front-end architectures and technologies for future reconfigurable mobile communication is given. A favourable solution for fourth mobile generation is an extension of traditional cellular parameters by OFDM-based systems like WLAN. Therefore, an approach for widely reconfigurable receivers considering a variety of different standards, with the example of combining WCDMA and WLAN front-end into one architecture, is presented in this paper. RF-front-end key components like low noise amplifiers, mixers, and frequency synthesizers, as well as baseband variable gain amplifiers and filters are treated, particularly with regard to reconfigurable systems.     

芯片的I/O新结构提高了传输带宽

芯片制造商AMD（AdvancedMicro Devices）（位于美国加州的Sunnyvale）协同它的合作伙伴,共同开发成功了一种新的I/O结构,命名为快速传输技术HTT（Hyper　TransportTechnology）。据称在现有总线结构基础上采用HTT,可以显著地提高传输带宽,同时还可以通过替换原有的总线与桥接器,简化内部的连接。HTT可以在线路板上,在IC之间提供点到点的高速链路,对于每一对线的信号传输速率可达1.6GHz,并且可以达到12.8 GB的     

Reconfigurable computing: a promising microchip architecture for artificial intelligence

Today,integrated circuit technology is approaching the physical limit.From performance and energy consumption perspective,reconfigurable computing is regarded as the most promising technology for future computing systems with excellent feature in computing and energy efficiency.From the perspective of computing performance,compared with single thread performance stagnation of general purpose processors(GPPS),reconfigurable computing may customize hardware according to application requirements,so as to achieve higher performance and lower energy consumption.From the perspective of economics,a microchip based on reconfigurable computing technology has post-silicon reconfigurability,which can be applied in different fields,so as to better share the cost of non-recurring engineering(NRE).High computing and energy efficiency together with unique reconfigurability make reconfigurable computing one of the most important technologies of artificial intelligent microchips.     

一种基ARM7的无线局域网 MAC片上系统架构

提出了一种ARM7TDMI核和先进微控制器总线架构的无线局域网MAC控制器片上系统方案,对各个组成模块进行了详细描述,并从设计复杂度、功耗、性能等方面对其该方案和其他方案进行了分析和比较.     

Current reliability issues and future technologies for systems on silicon – processes, circuits, chip architecture, and design

The progress of silicon technology is opening the era of “systems on silicon” in which a large-scale memory, a CPU, and other logic macros will be integrated on a single chip. These kinds of chips, called system LSIs, have an especially promising future in mobile and multimedia applications but face inherent technical problems related to the reliability of ultrathin oxide film, conflict in the processing of different components, increased gate and subthreshold leakage currents, memory bottlenecks, and design complexity. This paper reviews the system LSIs and then introduces related technologies in processing, circuits, chip architecture, and design. It also discusses the influence of the system LSIs on business strategies.     

未来移动通信网的位置服务体系结构

引 言位置服务(LCS)是未来无线移动通信网的一个组成部分。无论移动终端用户处于空闲或通话状态,这种新型的网络服务都能够将其地理定位。未来系统包括第三代(3G)系统(如UTRAN和IS-2000)以及现有系统(GSM,IS-95和IS-136)的增强型。此服务最初是为满足公共安全部门的规定。安全部门在其权限范围内,需     

Bus architecture of a system on a chip with user-configurablesystem logic

A bus architecture that provides high performance while scaling across a range of chip sizes is described. The system on a chip design in which it has been implemented includes both a dedicated processor with a set of embedded system peripherals and system support logic that may be reconfigured by a user in the field. Multiple masters and slaves are provided for in the architecture and included in the dedicated portion of this chip. Designers configure additional bus slave peripherals and support functions in the programmable logic. Dedicated structures extend the bus throughout the user-configurable system logic. The bus is pipelined, uses OR gates, and has separate read and write data. The bus pipeline registers are distributed to provide predictable performance and a synchronous interface to the designer. Bus protocol decoders are also distributed throughout the logic. These protocol decoders handle the complexities of pipelining for the designer. Virtual bus sockets provide all of the physical signals necessary to interface registers to the bus for single-cycle read and write transactions. The physical characteristics and design methods involved in the design of this system on a chip as well as those of the application environment all influenced the design tradeoffs in this architecture     

SIMD-systolic architecture and VLSI chip for computing the dynamic time-warping algorithm

A VLSI architecture, which exhibits both SIMD and systolic behaviour for computing the dynamic time-warping (DTW) algorithm is presented. Such an architecture is well-suited for VLSI implementation because of its regular structure and small number of input/output. Currently, based on a 1-2 µm CMOS technology, a SIMD-systolic data-path chip has been designed and fabricated for computing the DTW algorithm. It is functionally correct and packaged as a 68-pin PGA chip. With such a chip, a 20000-word real-time DTW-based speech recognition system is achievable.     

The architecture of a specific chip for RNA secondary structure prediction

The architecture of a BioAccel (internal code) chip for RNA secondary structure prediction is described in the letter. The system is based on a BioBus (internal code), whose distinguishing features are: Two separated control and data channels, and a slave-associated arbitration scheme. Two reference systems based on the AMBA AHB bus and Coreconnect bus are introduced to evaluate the performance of the system. The simulation results are attractive.The average communication bandwidth of the chip is increased at severalfold, and the read and write latencies are reduced about 40 percent.     

未来物联网应用的软件架构研究

物联网应用涉及众多领域,文中分析了物联网的起源和发展现状,物联网涉及的软硬件设施多、范围广,详细研究了未来物联网应用的软件架构,提出了一种设备独立的物联网应用软件架构,通过中间件技术将物联网各种软件应用和硬件设备进行有效隔离,实现了物联网灵活高效的应用服务。