Compact thermal networks for modeling packages

In this paper, thermal networks for modeling packages are rigorously introduced. A multipoint moment matching method for state space reduction of these discretized thermal networks is formulated. In this manner reduced thermal networks are derived that can be used as boundary condition independent compact thermal models of packages. This algorithm is successfully applied to the detailed analysis of an idealized ball grid array package.     

The thermal modeling of integrated-circuit device packages

Heat elimination from power integrated-circuit packages represents an ever present problem due to the highdegree of dissipation of energy emitted from high-voltage devices. An important consideration in the removal of large quantities of heat is the choice of material for the heat sink and its geometric configuration. The amount of copper used as a heat sink is limited by economic factors. An engineering model has been developed to estimate the dimensions of the heat sink based on a simple one-dimensional multilayer steady-state heat transport model. The model shows that the transport of energy from the heat sink to the ambient is a weak function of the thickness. On the other hand, the areal dimensions play a major role in the efficiency of heat transfer across the surface. Beyond a ratio of 4 (length/ width), efficiency of heat transport is not measurably increased. A transient analysis was included to see if time dependencies influenced the progress of heat flow.     

适用于IC封装的表面涂覆层——化学镀镍、钯、金的未来

概述了化学镀镍/化学镀钯/浸金涂（镀）覆层的优点,它比起化学镀镍/浸金,不仅更适用于IC封装,而且提高了可靠性,降低了成本。     

Interface delamination in plastic IC packages induced by thermal loading and vapor pressure - a micromechanics model

A micromechanics model and an associated computational scheme are proposed to study interface delamination in plastic integrated circuit (IC) packages induced by thermal loading and vapor pressure. The die and die-pad are taken as elastic materials, while the die-attach and molding compound are taken as elasto-visco-plastic materials. The interface between molding compound and the die-pad is characterized by a cohesive law. The key parameters of this law are the interface strength and interface energy. The vapor-induced pressure along the interface is incorporated by way of a micromechanics model. Parametric studies are conducted to understand interface properties and vapor pressure effects on interface delamination. Under purely thermal loading, both weak and strong interfaces are highly resistant to interface failure. However, the combined effects of thermal loading and vapor pressure arising from moisture trapped within the interface can cause total delamination at the interface. Once delamination has initiated at a weak interface, no significant increase in thermal loading and vapor pressure is required for the delaminated zone to grow to a macro-crack and subsequently to catastrophic failure referred to as popcorn cracking. The critical factors controlling the occurrence of popcorn cracking are the interface adhesion strength and interface vapor pressure.     

Assembly-level reliability: a methodology for effectivemanufacturing of IC packages

This paper discusses the general methodology of assembly level reliability (ALR) as part of a corporate effort at designing reliability into the whole assembly process of integrated circuit (IC) packages. Semiconductor packages with assembly-induced defects sometimes do escape detection due to a variety of reasons. Trying to eliminate this problem by approaching it piecemeal may result only in single process optimization, but does not guarantee full assembly line balancing for error-free production. ALR is a systematic 4-prong approach which uses a combination of techniques for synergistic effects. (1) Problems of immediate needs have to be addressed and contained, (2) The proper steps must then be taken to ensure that similar issues do not resurface. (3) Design-for-manufacturability principles must be applied; e.g., the design of the package can be simplified to reduce the number of assembly steps, increase throughput, and cut cost. (4) Qualification methodologies have to be revisited. Less expensive but well-characterized test chips can be introduced in lieu of actual devices. Accelerated testing with a good understanding of the failure mechanisms facilitates faster product qualification to ensure time-to-market advantage. Together with these more cost-effective qualification techniques, the proper reliability-monitoring features must be installed. Only then can the true vision of ALR be accomplished, viz, ensuring recognition, by both customers and competitors, as a Company that continuously manufactures defect-free parts     

Dynamic thermal characterization and modeling of packagedAlGaAs/GaAs HBTs

In this work we show a method for the thermal dynamic modeling of packaged HBTs. The method employs a calibration step featuring pulsed measurements at different temperatures, and is based upon a 3-stage thermal resistance-capacitance model that describes the chip-solder-case system. A current pulse generator was designed and assembled in-house for pulsed characterization down to the microsecond range. The model was used to simulate the thermal transients of the collector current from the microsecond range to hundreds of seconds, for several different bias points in the forward active region, consistently showing a good match with the measured characteristics     

Complete methodology for electrical modeling of RFIC packages

A complete methodology based on broadband S-parameter measurement is proposed to establish the electrical models for radio-frequency integrated circuit (RFIC) packages. The research is focused on calibration of the test-fixture parasitics to obtain the intrinsic S-parameters from which an equivalent coupled lumped model can be extracted for any pair of package leads under test. Then a step-by-step optimization scheme is employed to construct an equivalent circuit for the whole package. A real example on modeling a 16-lead Thin Shrink Small Outline Package (TSSOP) has been demonstrated. The established model can account for various package effects at radio frequencies     

A method of the measurement of moisture in IC packages using microwaves

A new method to measure the moisture content of integrated circuit (IC) packages is demonstrated. The moisture contained in the encapsulant resin was determined by using microwaves. The microwave signal was transmitted into the encapsulant resin and reflected at the surface of the chip pad. The amplitude and phase of the reflection coefficient of the microwave signal, which varied with the moisture content of the encapsulant resin, were measured in order to determine the moisture content. A preliminary experiment was carried out, and the calibration equation was developed. The present technique indicates the possibility of determining the moisture content directly without drying and weighing IC packages.     

Effect of stiffness and thickness ratios on popcorn cracking in IC packages

During the solder reflow process, popcorn cracking will occur in integrated circuit (IC) package under vapor pressure and thermal load. Based on the elasticity theory, the singular stress field around the apex of the delaminated interface between die-pad and resin is obtained numerically. The generalized stress intensity factors are computed to evaluate the residual strength of the structure. Also, the structural stability is discussed by using the strain energy density theory. Two factors that are concerned in this paper include the relative stiffness ratio E/sub die-pad//E/sub resin/ and the relative thickness h~. The results show that lower stiffness ratio gives weaker stress singularity. In addition, larger h~ will increase generalized stress intensity factors and structural stability. As a conclusion for our case, moderate value of h~ (say h~=0) is recommended for design.     

Drop impact reliability testing for lead-free and lead-based soldered IC packages

Board-level drop impact testing is a useful way to characterize the drop durability of the different soldered assemblies onto the printed circuit board (PCB). The characterization process is critical to the lead-free (Pb-free) solders that are replacing lead-based (Pb-based) solders. In this study, drop impact solder joint reliability for plastic ball grid array (PBGA), very-thin quad flat no-lead (VQFN) and plastic quad flat pack (PQFP) packages was investigated for Pb-based (62Sn–36Pb–2Ag) and Pb-free (Sn–4Ag–0.5Cu) soldered assemblies onto different PCB surface finishes of OSP (organic solderability preservative) and ENIG (electroless nickel immersion gold). The Pb-free solder joints on ENIG finish revealed weaker drop reliability performance than the OSP finish. The formation of the brittle intermetallic compound (IMC) Cu–Ni–Sn has led to detrimental interfacial fracture of the PBGA solder joints. For both Pb-based and Pb-free solders onto OSP coated copper pad, the formation of Cu₆Sn₅ IMC resulted in different failure sites and modes. The failures migrated to the PCB copper traces and resin layers instead. The VQFN package is the most resistant to drop impact failures due to its small size and weight. The compliant leads of the PQFP are more resistant to drop failures compared to the PBGA solder joints.     

Characterization of radiation loss from microstrip discontinuitiesusing a multiport network modeling approach

A convenient method for evaluating radiation loss from microstrip discontinuities is presented. A planar multiport network model of the discontinuity configuration and the segmentation method are used to evaluate the voltage distribution around the edges of the discontinuity. This voltage distribution is expressed as an equivalent magnetic current line source distribution which is used to calculate the far-zone field (for radiation loss). As an example, the results show that for a 90° bend in a 50-Ω line on a 10-mil-thick substrate with ϵ_r =2.2, the radiation loss is 0.1 dB at 30 GHz. Typical power levels radiated by several other discontinuities are reported. The analysis model was verified experimentally by fabricating microstrip resonators with discontinuities incorporated therein and measuring the Q factors of these resonators     

Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling

Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing value for the dielectric constant k. These so-called (ultra) low-k materials have a reduced stiffness and reduced adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied mechanical stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC’s use thinned dies (down to 25 μm) which can cause much higher stresses at transistor level, resulting in electron mobility shifts of the transistors. Also the copper TSV (through-silicon-via) generates local stress which affects the device performance. This paper considers both the packaging impact on BEOL integrity and transistor mobility shifts for 3D stacked IC (integrated circuit) technologies.     

Experimental and statistical study in adhesion features of bonded interfaces of IC packages

The existence of defects in the corresponding interfaces can gradually degrade the interfacial adhesion when the flip chip package is exposed to the high temperature and humidity. This study used the fuzzy controller to stabilize both the moisture weight gain and adhesion strength together for the button shear test specimen. Parameters design, although based on the Taguchi method, can optimize the performance characteristic through the setting of process parameters and can reduce the sensitivity of the system performance to sources of variation. However, most published Taguchi applications to date have been concerned with the optimization of a single performance characteristic only. For example, it is only concerned a single performance characteristic with the optimization of the adhesion strength or the moisture gain weight individually. In this study, the control rules of the fuzzy controller were formed using the authors’ experience and knowledge of the IC packaging process. The control parameters to be tuned were the membership functions. Therefore, the controller’s performance depended on the membership functions. The fuzzy controller combined Taguchi parameter design, which makes the control performance insensitive to the operating condition changes and noise was used to determine the membership functions.     

Die stress drift measurement in IC plastic packages using the piezo-Hall effect

A method for encapsulation stress drift measurement based on the piezo-Hall effect is proposed. Accuracy of ±0.25 MPa for the sum of in-plane normal stresses is achieved. Using this method, the drift of die stress in IC plastic packages has been measured after temperature cycling. Stress relaxation with the time constant of about one day has been observed.     

A simple model for the mode I popcorn effect for IC packages

A simple model for the Mode I popcorn effect is presented here for packages with rectangular die pad (P-DSO). A package “stability parameter”, relating to its moisture sensitivity, is derived from the popcorn model. It describes the critical factors for a robust package - molding compound properties and package, leadframe design for a given preconditioning and soldering process. Furthermore, nomograms generated from the model enable an easy estimation of moisture sensitivity levels (between 1 and 5) of packages with different die pad sizes and molding compound underpad thicknesses and for different soldering temperatures ranging from 220°C to 260°C (Pb-free soldering).     

Determination of temperature change inside IC packages during laser ablation of molding compound

In addition to chemical jet etch method, decapsulation performances of electronic packages for failure analysis are virtually enhanced using lasers. Nevertheless circuits inside package could be subjected to a local thermal elevation during the package ablation process. In this paper, we introduce an innovative technique to measure the thermal behavior of an encapsulated system in situ and in real time during laser decapsulation. Measurements of the heat elevation during ablation process in the three regions of interest for failure analysis are discussed: over IC, bonding and lead-frame.     

An overview of electrical characterization techniques and theory for IC packages and interconnects

This paper reviews current approaches to the electrical characterization and modeling of IC packages and interconnects. An overview of both frequency and time-domain measurement methods and summaries of equivalent circuit model selection and extraction methodologies are included. Additionally, an overview of numerical methods for electromagnetic modeling is included for completeness. Finally, relevant case studies from the literature are summarized to further supplement the discussed techniques. The focus is primarily on high-frequency signal related characterization and power integrity issues are not directly considered in this paper. This paper is presented in the context of the growing requirement for package and interconnection electrical models for high-speed and miniaturized systems.     

MOSFET modeling for RF IC design

High-frequency (HF) modeling of MOSFETs for radio-frequency (RF) integrated circuit (IC) design is discussed. Modeling of the intrinsic device and the extrinsic components is discussed by accounting for important physical effects at both dc and HF. The concepts of equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model. The procedures of the HF model parameter extraction are also developed. A subcircuit RF model based on the discussed approaches can be developed with good model accuracy. Further, noise modeling is discussed by analyzing the theoretical and experimental results in HF noise modeling. Analytical calculation of the noise sources has been discussed to understand the noise characteristics, including induced gate noise. The distortion behavior of MOSFET and modeling are also discussed. The fact that a MOSFET has much higher "low-frequency limit" is useful for designers and modelers to validate the distortion of a MOSFET model for RF application. An RF model could well predict the distortion behavior of MOSFETs if it can accurately describe both dc and ac small-signal characteristics with proper parameter extraction.     

IC process modeling and topography design

The device features in the third dimension in VLSI affect packing density and circuit performance. Establishing techniques to characterize and design these nonplanar device features is a major goal of the research on IC process modeling and simulation. Simulation is well accepted as a means of optimizing individual lithography, etching, and deposition processes. It is also well suited for studying the complex tradeoffs between conflicting physical mechanisms in the context of complete multistep process sequences. The success of modeling and simulation has created a demand for more extensive models and new applications. IC process modeling and simulation will not only contribute heavily to technology design but also offers a potential window through the layout role bottleneck for more complete design insight and optimization.     

Compact thermal models of packages used in conduction cooledapplications

Results of an extensive study aimed at developing boundary condition independent compact steady-state thermal models of a variety of electronic packages used in conduction cooled applications are presented. Formal mathematical principles were used to establish a nonredundant set of thermal boundary conditions representing board edge and backside cooling with variable board and underfill conductivity. A Design of Experiments approach was employed to reduce the total number of boundary conditions to four, allowing the generation of boundary condition independent CTM's. Two general network topologies, incorporating both simple star-shaped and more complex, shunted networks were developed. To extract the CTM parameters, the thermal networks were optimized using a genetic algorithm-based approach allowing constrained nonlinear global optimization in a standard spreadsheet environment. Comparisons of the accuracy of models from simple to complex are presented for two types of generic parts. It was found that optimized star-shaped CTM's accurately predict junction temperatures, but usually give insufficient accuracy for the heat flows leaving via the package prime lumped surfaces. The inclusion of a floating node allows sufficient degree of freedom to correctly redistribute the heat flows between the “outlet” nodes of the networks. Using the optimization technique, CTM's were derived for thirty parts representing thirteen package families. For most of the packages only network topologies that included a floating node and surface-to-surface links provided satisfactory accuracy. With three different network configurations, for which examples are presented, it was possible to capture the thermal behavior of all the package families investigated