High-speed low-power cross-coupled active-pull-down ECL circuit

This paper presents a high-speed low-power cross-coupled active-pull-down ECL (CC-APD-ECL) circuit. The circuit features a cross-coupled active-pull-down scheme to improve the power-delay of the emitter-follower stage. The cross-coupled biasing scheme preserves the emitter-dotting capability and requires no extra biasing circuit branch and power for the active-pull-down transistor. Based on a 0.8 μm double poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 1.7× improvement in the loaded (FI/FO=3, C_L=0.3 pF) delay, 2.1× improvement in the load driving capability, and 3.5× improvement in the dotting delay penalty compared with the conventional ECL circuit. The design considerations of the circuit are discussed     

High-speed low-power charge-buffered active-pull-down ECI circuit

A high-speed, low-power, charge-buffered active-pull-down ECL (emitter-coupled logic) circuit is described. The circuit features a charge-buffered coupling between the common-emitter node of the switching transistors and the base of an active-pull-down n-p-n transistor. This coupling scheme provides a much larger dynamic current than what can be reasonably achieved through the capacitor coupling and a DC path to alleviate the AC-testing requirement. Furthermore, the dynamic current is utilized effectively by the logic stage, thus allowing a reduction in the power consumption of the logic stage without sacrificing the switching speed. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 37% improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed     

An ECL gate with improved speed and low power in a BiCMOS process

An emitter-coupled logic (ECL) gate exhibiting an improved speed-power product over the circuits presented in the past is described. The improvement is due to a combination of a push-pull output stage driven by a controlled current source, thus reducing the static and increasing the dynamic current. This circuit has better driving capabilities and improved speed, yet it uses an order of magnitude less power than a regular ECL gate. Due to its reduced power consumption, this gate allows for a higher level of integration of ECL logic. The realization of this circuit using a regular bipolar process is also possible     

Capacitor-free level-sensitive active pull-down ECL circuit withself-adjusting driving capability

This paper introduces a new self-adjusting active pull-down scheme for ECL circuit. The circuit offers self-terminating dynamic pull-down action by sensing the output level rather than using traditional load-dependent capacitive coupling. No capacitor or large resistor is required, and therefore it adds no process complexity and no area penalty. Implemented in an ECL gate array in a 1.2 μm double-poly self aligned bipolar technology, the circuit offers 300-ps delay at a power consumption of 1 mW/gate under FO=1 and C_L=0.55 pF loading condition. This is a 4.4 times speed improvement over the conventional ECL circuit. Furthermore, the circuit consumes only 0.25 mW for a gate speed of 700 ps/gate, which is a 1/7.8 power reduction compared with the conventional ECL circuit. The circuit requires a regulated reference voltage, which is also studied     

Active-pull-down nonthreshold logic BiCMOS circuits for high-speedlow-power applications

A new active-pull-down nonthreshold logic (APD-NTL) BiCMOS circuit is presented and its performance has been evaluated and compared to that of standard NTL gate. The circuit utilizes an NMOS active-pull-down emitter-follower stage. A first-order analysis has been conducted to demonstrate the NMOS-APD concept. Simulation results based on 0.6 μm BiCMOS technology indicate that at a power consumption of 1 mW/gate, the APD-NTL circuit offers 4× improvement in the load driving capability and 3.4× improvement in the speed compared to conventional NTL circuits for a load of 1 pF/gate and a logic swing of 800 mV     

A self-biased feedback-controlled pull-down emitter follower forhigh-speed low-power bipolar logic circuits

A feedback-controlled active-pull-down emitter follower that is self-biased at a low steady-state current and allows the collector dotting and emitter dotting is proposed for high-speed low-power bipolar/BiCMOS digital logic circuits. The push-pull operation of this emitter follower is precisely controlled by a feedback mechanism and does not require any extra out-of-phase signal other than the emitter-follower input from the logic stage. Simulation results based on a 0.5-μm advanced Si-bipolar technology show that the pull-down delay and drive capability of a loaded 1-mW feedback-controlled pull-down ECL gate are improved to the pull-up levels, 2.7 and 10 times better than those of the conventional resistor-pull-down ECL circuit, respectively     

Non-quasi-static effects in advanced high-speed bipolar circuits

A detailed study on the non-quasi-state (NQS) effects in advanced high-speed bipolar circuits is presented. An NQS Gummel-Poon-compatible lumped circuit model, which accounts for carrier propagation delays across various quasi-neutral regions in bipolar devices, is implemented in the ASTAP circuit simulator. The effects are then evaluated and compared with those for the conventional Gummel-Poon model for the emitter-coupled logic (ECL) circuit, the non-threshold-logic (NTL) circuit, and various advanced circuits utilizing active-pull-down schemes. For the ECL circuit, the effect decreases with reduced power level and increased loading. For the NTL circuit, due to its front-end configuration, the effect is more significant than that for the ECL circuit but tends to increase with reduced power level. As the passive resistors (and the associated parasitic RC effect) are decoupled from the delay path and the circuit delay is made more intimately related to the intrinsic speed of the devices in various advanced active-pull-down circuits, the delay degradation due to NQS effect becomes more significant     

High-speed low-power direct-coupled complementary push-pull ECLcircuit

This paper presents a high-speed low-power direct-coupled complementary push-pull ECL (DC-PP-ECL) circuit. The circuit features a direct-coupled pnp pull-up and npn pull-down scheme with no extra biasing circuit for the push- and pull-transistor. The bias of the pull-up pnp transistor is established entirely by direct tapping of the existing voltage levels in the current switch. The scheme provides a sharp self-terminating dynamic current pulse through the pull-up pnp transistor during the switching transient, thus completely decoupling the collector load resistor from the delay path. Based on a 0.8-μm double-poly self-aligned complementary bipolar process, the circuit offers 2.0X (2.2X) improvement in the loaded delay at 1.0 (0.5) mW/gate and 2.2X improvement in the load driving capability at 1.0 mW/gate compared with the conventional ECL circuit     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

12.8-ps 1.0-mW charge-buffered active pull-down NTL circuit

An NTL circuit with a charge-buffered active-pulldown emitter-follower stage is described. The circuit utilizes the diffusion capacitance of a charge-storage diode (CSD) as the coupling element between the common-emitter node of the switching transistors and the base of an active-pull-down n-p-n transistor to generate a large dynamic current for the pull-down transistor and to provide a speedup effect on the switching logic stage. Implemented in a 0.8-μm double-poly trench-isolated self-aligned bipolar process, unloaded gate delays of 12.8 ps/1.0 mW, 15.4 ps/0.71 mW, and 18.0 ps/0.53 mW have been achieved     

On the leverage of high-fT transistors foradvanced high-speed bipolar circuits

A detailed study on the leverage of high-f_T transistors for advanced high-speed bipolar circuit applications is presented. It is shown that for the standard ECL (emitter-coupled logic) circuit, the leverage of high f_T is limited by the passive resistors (emitter-follower resistor and collector load resistor) and wire delay, especially in the low-power regime. For the standard NTL (nonthreshold logic) circuit, the leverage is higher due to its front-end configuration and lower power supply value. As the passive resistors are decoupled from the delay path in various advanced circuits utilizing active-pull-down schemes, the leverage of high F_T becomes more significant     

3.21 ps ECL gate using InP/InGaAs DHBT technology

A new circuit configuration for an emitter-coupled logic (ECL) gate that can reduce propagation delay time has been demonstrated. Nineteen-stage ring oscillators were fabricated using InP/InGaAs double-heterojunction bipolar transistors (DHBTs) with cutoff frequency f/sub T/ and maximum oscillation frequency f/sub max/ of about 232 and 360 GHz, respectively, to evaluate the speed performance of the proposed ECL gate. The minimum propagation delay is 3.21 ps/gate. The proposed ECL gate is about 8% faster than the conventional ECL gate.     

A high speed GaAs error-detection circuit for fiber-optictransmission systems

A high-speed GaAs IC for detection of line code vibrations is described. This 144-gate error-detection circuit for monitoring a high-bit-rate fiber-optic link has been designed and fabricated using a high-yield titanium tungsten nitride self-aligned gate MESFET process. This process routinely provides a wafer-averaged gate delay (fan-in=fan-out=2) of less than 70 ps with a power dissipation of 0.5 mW/gate. The error-detection circuits were tested on-wafer using high-frequency probe cards at a clock rate of 1.4 GHz, with a yield of 64%. Packaged circuits worked at a clock frequency of over 2.5 GHz and consumed 200-mW power at a fixed power supply voltage of 1.5 V. The circuits operate over a wide variation in power supply voltage and temperature. When operated at a package temperature of 125°C, the circuits show less than a 12% degradation in their maximum clock frequency. The circuit was inserted into a 565-Mb/s system currently using a silicon ECL part, and full functionality was verified with no necessary modifications     

A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage

An emitter-coupled logic (ECL) gate with an AC-coupled active pull-down emitter-follower stage that gives high speed at lower power is described. Significant reduction of the speed-power product can be achieved over the conventional ECL gate. The speed/power advantages of the circuit have been demonstrated in a double-poly, trench-isolated, self-aligned bipolar process with 0.8- mu m (mask) emitter width. Unloaded gate delays of 21 ps at 4.1 mW/gate, 23 ps at 2.1 mW/gate, and 35 ps at 1.1 mW/gate have been measured.<>     

An ultra-high-speed ECL-BiCMOS technology with silicon filletself-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 μm gate and 50 ps on 0.6 μm gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 μm emitter ring oscillators with collector current density of 40 kA/cm². A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

Diode-HBT-logic circuits monolithically integrable with ECl/CMLcircuits

A novel logic approach, diode-HBT logic (DHL), that is implemented with GaAlAs/GaAs HBTs and Schottky diodes to provide high-density and low-power digital circuit operation is described. This logic family was realized with the same technology used to produce emitter-coupled-logic/current-mode-logic (ECL/CML) circuits. The logic operation was demonstrated with a 19-stage ring oscillator and a frequency divider. A gate delay of 160 ps was measured with 1.1 mW of power per gate. The divider worked properly up to 6 GHz. Layouts of a DHL flip-flop and divider showed that circuit area and transistor count can be reduced by about a factor of 3, relative to ECL/CML circuits. The new logic approach allows monolithic integration of high-speed ECL/CML circuits with high-density DHL circuits with high-density DHL circuits     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

Bipolar high-speed low-power gates with double implanted transistors

Speed power relations oxide isolated double implanted subnanosecond gate circuits (ECL and E/SUP 2/CL) were investigated in comparison to double diffused circuits. Under optimizing aspects with respect to propagation delay, data of double implanted integrated bipolar transistors and circuit performance are given dependent on implantation parameters.