Short-channel MOSFET VT-VDScharacteristics model based on a point charge and its mirror images

Short-channel MOS transistordV_{T}/dV_{DS}characteristics are expressed by an analytic function of fundamental device parameters. The expression is derived from a simple model of short-channel MOS transistors in threshold condition, which is based on a point charge and its mirror images. With this expression,dV_{T}/dV_{DS}is found to be proportional to1/L^{2}-1/L^{4}, whereLis channel length. Following factors are also found, wherein the source and drain junction depth effect is only logarithmic ondV_{T}/dV_{DS}characteristics,dV_{T}/dV_{SUB}anddV_{T}/dV_{DS}are closely related in short-channel MOS transistors, and short-channel effects are expected to be smaller in MOS transistors on SOS than on bulk silicon, due to a large number of Si/sapphire interface states. This model is simple, and it can be applied to short-channel MOS transistor designing and circuit simulations.     

Improved subthreshold characteristics of n-channel SOI transistors

It has been found that certain n-channel MOSFET's fabricated on silicon-on-insulator (SOI) substrates formed by oxygen implantation can havelog (I_{d}): V_{gs}, characteristics with very steep slopes in the subthreshold region. In contradiction to normal models for short-channel transistors on bulk silicon, the slope becomes steeper for shorter gate lengths or higher drain voltages. This effect is shown to be related to the kink in the output characteristics of transistors with floating islands.     

Subthreshold conduction in silicon-on-sapphire transistors

The subthreshold conduction in silicon-on-sapphire MOS transistors has been studied both theoretically and experimentally. A simple model to describe the subthreshold conduction current for both thick films and thin films is derived in terms of charges in the silicon and charges at the silicon-silicon dioxide and silicon-sapphire interfaces. The model has been extended to cover short-channel transistors by application of charge conservation under the channel region. It is shown that the subthreshold conduction current for a SOS-MOS transistor has a form similar to that found in bulk transistors, but with modification of the terms due to the finite silicon film thickness and the unique geometry of the SOS-MOS transistor. The general form of the model has been confirmed by measurement of the subthreshold current on several hundred SOS-MOS transistors of different geometries manufactured by various companies.     

Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGeheterostructure channel

Thin-body p-channel MOS transistors with a SiGe/Si heterostructure channel were fabricated on silicon-on-insulator (SOI) substrates. A novel lateral solid-phase epitaxy process was employed to form the thin-body for the suppression of short-channel effects. A selective silicon implant that breaks up the interfacial oxide was shown to facilitate unilateral crystallization to form a single crystalline channel. Negligible threshold voltage roll-off was observed down to a gate length of 50 nm. The incorporation of Si_0.7Ge_0.3 in the channel resulted in a 70% enhancement in the drive current. This is the smallest SiGe heterostructure-channel MOS transistor reported to date. This is also the first demonstration of a thin-body MOS transistor incorporating a SiGe heterostructure channel     

Sub-quarter-micrometer CMOS on ultrathin (400 Å) SOI

MOS transistors with effective channel lengths down to 0.2 μm have been fabricated in fully depleted, ultrathin (400 Å) silicon-on-insulator (SOI) films. These devices do not exhibit punchthrough, even for the smallest channel lengths, and have performance characteristics comparable to deep-submicrometer bulk transistors. The NMOS devices have a p⁺-polysilicon gate, and the PMOS devices have an n⁺-polysilicon gate, giving threshold voltages close to 1 V with very light channel doping. Because the series resistance associated with the source and drain regions can be very high in such thin SOI films, a titanium salicide process was used using a 0.25 μm oxide spacer. With this process, the sheet resistance of the silicided SOI layer is approximately 5 Ω/□. However, the devices still exhibit significant series resistance, which is likely due to contact resistance between the silicide and silicon source/drain regions     

Direct capacitance measurements of small geometry MOS transistors

Methods for measuring the intrinsic capacitances of small geometry MOS transistors are described. The influence of short- and narrow-channel effects on the capacitance characteristics of MOS transistors is evaluated. The results are compared with long-channel devices. It is shown that the presented capacitance methods can be used to study the physics of short-channel transistors.     

Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs

We have investigated short-channel effects of ultrathin (4-18-nm thick) silicon-on-insulator (SOI) n-channel MOSFET's in the 40-135 nm gate length regime. It is experimentally and systematically found that the threshold voltage (V_th) roll-off and subthreshold slope (S-slope) are highly suppressed as the channel SOI thickness is reduced. The experimental 40-nm gate length, 4-nm thick ultrathin SOI n-MOSFET shows the S-slope of only 75 mV and the ΔV_th of only 0.07 V as compared to the value in the case of the long gate-length (135 nm) device. Based on these experimental results, the remarkable advantage of an ultrathin SOI channel in suppressing the short-channel effects is confirmed for future MOS devices     

A new five-parameter MOS transistor mismatch model

A new five-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation regions, including short-channel transistors. The new model is based on splitting the contribution of the mobility degradation parameter mismatch Δ&thetas; into two components, and modulating them as the transistor transitions from ohmic to saturation regions. The model is tested for a wide range of transistor sizes (30), and shows excellent precision, never reported before for such a wide range of transistor sizes, including short-channel transistors     

Modeling of the 1/f noise overshoot in short-channel MOSFETs locally degraded by hot-carrier injection

On the basis of previous results concerning the 1/f noise in electrically stressed MOS transistors and the characterization of aged MOSFETs, the authors present a theoretical model for the flicker noise in nonhomogeneous short-channel MOS transistors operated in the ohmic region. When applied to hot-carrier-induced degradation, a simple two-region approximation of this model is shown to account for the existence of a noise peak (overshoot) near the threshold voltage, similar to the transconductance overshoot already observed. A two-dimensional simulation makes it possible to detail the influence of the gate bias, the distance over which the interface states (or traps) are generated, and their density. The 1/f noise overshoot appears to be more sensitive to aging conditions than transconductance overshoot.<>     

Substrate Bias Effect Linked to Parasitic Series Resistance in Multiple-Gate SOI MOSFETs

It is generally recognized that very narrow silicon-on-insulator (SOI) fin field-effect transistors (FinFETs) are insensitive to substrate bias due to the strong electrostatic gate control. In this letter, we demonstrate, for the first time, that, in short-channel narrow FinFETs, substrate bias can dramatically change the on-current without change in the threshold voltage, subthreshold slope, and drain-induced barrier lowering, due to the modulation of the parasitic series resistance. Therefrom, contrary to general belief, very narrow short-channel multiple-gate field-effect transistors can be sensitive to substrate-related effects (buried oxide formation, irradiation, etc). Another important implication of the described effect is related to the diagnostics of the series resistance in SOI FinFETs and better prediction of their full intrinsic performance potential.     

A CPD image sensor with an SOI structure

A CPD image sensor with an SOI (silicon-on-insulator) structure has been developed. The sensor is composed of read-out transistors fabricated on laser-recrystallized silicon, photodiodes on the seeding region, an MOS shift register, and a CCD shift register. A reproduced image with a 50 (H)×60 (V) pixel image sensor showed reduction of smear noise to a value 1/8000 times that in the bulk transistor as a result of complete isolation of the drains of the read-out transistors by oxide layers     

Modes of operation and radiation sensitivity of ultrathin SOItransistors

Improved short-channel behavior, reduced subthreshold slopes, and mobility enhancements previously observed in NMOS transistors made in thin, fully depleted silicon-on-insulator (SOI) films are discussed. These results were obtained with the back interface held in depletion during operation. It is shown from basic principles of device operation that the observed performance improvements are sensitive to the applied substrate voltage. In addition, the exposure of the back interface to the surface depletion region in these devices makes the transistor performance sensitive to radiation-induced charging effects at the back interface. The anticipated effects of radiation on threshold voltage, subthreshold slope, and mobility in ultrathin, fully depleted SOI transistors are discussed, and an estimate is made of the expected radiation sensitivity of these parameters for a typical ultrathin SOI technology     

Sub-threshold leakage currents in weakly inverted short channel IGFETS

This paper attempts to develop a comprehensive device model suitable for computer aided design, in the sub-threshold mode of operation, for short-channel insulated-gate field-effect transistors (IGFETs). It is shown that, for state-of-the art MOS LSI, employing 4–6 μ channel length devices, the sub-threshold conduction current is influenced by the longitudinal electric field to a significant degree. The device model is found to be in close agreement with experimental data. The limitations of this model for very short channel IGFETs is briefly discussed.     

Noise in DMOS transistors in a BICMOS-technology

An experimental and theoretical study of the 1/f noise and the thermal noise in double-diffused MOS (DMOS) transistors in a BICMOS-technology has been carried out. By using an analytical model that consists of an enhancement MOS transistor in series with a depletion MOS transistor and a resistance, and by attributing noise sources to each device, the noise in DMOS devices is simulated accurately. Three distinct regions of operation are defined: enhancement transistor control, depletion transistor control and the linear region. In the first region, the noise is strictly determined by the enhancement transistor. It was found that the 1/f noise in this region is caused by mobility fluctuations and is very low. In the depletion transistor control region both transistors influence the total noise. Here the 1/f noise is dominated by the depletion transistor. The series resistance is only of importance in the linear region     

A simple approach for accurately modeling the threshold voltage of short-channel mosts

We present a theory which models short-channel effects in MOS transistors (MOST). Our approach accounts for the effects of the source and drain depletion regions on the energy band configuration and the effective depletion layer charge under the channel. We derive an equation for low drain bias threshold voltage which accurately predicts the measured threshold on devices ranging in size from very small (1.5 μm) to very large (100 μm) effective channel lengths. The equation reliably predicts the phenomenon of decreasing threshold voltage and body effect observed experimentally from devices of decreasing channel length. The equation is valid for any bulk silicon MOS technology provided that the substrate doping is approximately uniform (i.e. ion-implantation has not been used to adjust the threshold). Our approach can be applied directly to the modeling of the short-channel drain to source current. This application of the theory will be presented in a later paper.     

Increased drain saturation current in ultra-thinsilicon-on-insulator (SOI) MOS transistors

Based on substrate-charge considerations, an increased drain saturation current for MOS transistors in ultrathin silicon-on-insulator (SOI) films is predicted, compared to similar transistors in bulk or thick SOI films. For typical parameters of 200-A gate oxide with a channel doping of 4×10¹⁶ cm^-3, the drain saturation current in ultrathin SOI transistors is predicted to be ~40% larger than that of bulk structures. An increase of ~30% is seen in measurements made on devices in 1000-A SOI films     

Current gain high-frequency CMOS operational amplifiers

The performance of high unity gain-bandwidth current gain-based CMOS operational amplifiers fabricated in a 1.5-/spl mu/m CMOS digital process is discussed. High unity-gain bandwidth was achieved by using short-channel MOS transistors operating in the current gain mode. Stacked current mirrors have been utilized as current gain stages to minimize the effects of the channel-length modulation in short-channel MOS transistors. Open-circuit gain of 60 to 70 dB, a unity-gain bandwidth of 70 to 100 MHz, and slew-rate of 200 V//spl mu/s were demonstrated at a DC power dissipation of 1-2 mW.     

Large-signal linearity of scaled MOS transistors

The tendency toward linearity between saturated drain current and gate-to-source voltage exhibited by small-dimension MOS transistors is explored from the standpoint of possible exploitation in analog MOS circuits. Nonlinearity is calculated using a simple MOS model which includes the high field dependence of inversion-layer carrier mobility. The nonlinearity for devices with a wide range of channel lengths and gate dielectric thicknesses was measured and is compared to results from the model. Some problems associated with the use of short-channel MOS transistors in analog circuits are discussed.     

Silicon-on-nothing MOSFETs: performance, short-channel effects, and backgate coupling

Silicon-on-nothing (SON) transistors with gate length varying from 0.25 /spl mu/m down to 80 nm exhibit excellent performance and scalability. The silicon-on-insulator (SOI)-like architecture with thin fully depleted Si film and ultrathin buried oxide results in attenuated short-channel effects (charge sharing, DIBL and fringing fields), high current, and electron mobility. A new model accounts for the intrinsic mechanisms of operation in SON MOSFETs: i) substrate depletion governed by source and drain via doping modulation, ii) relatively low coupling between the front- and backgates, iii) role of ultrathin buried oxide. The proposed model reproduces the variations of the threshold voltage and subthreshold swing and is useful for further device optimization.     

Electrical characteristics of a DSA MOS transistor with a fine structure

Fabrication technologies and electrical characteristics of a diffusion self-aligned MOS transistor (DSA MOST) or a double-diffused MOS transistor (DMOST) are discussed in comparison with a conventional short-channel MOS transistor as a fundamental device for a VLSI. The symmetrical DSA MOS LSI with enhancement depletion configurations requires six photolithographic steps and the number of the steps is the same as that of an NMOS LSI with small physical dimensions. The only difference is the step orders of the enhancement channel doping in these devices. The lowering effects of the threshold voltage and the source drain breakdown voltage are smaller in the DSA MOST than in the conventional MOS transistor. The drain current IDof the symmetrical DSA MOS transistor is, respectively, 1.13 (in the nonsaturation region) and 1.33 (in the saturation region) times larger than that of the conventional short-channel NMOS transistor at the effective gate voltage of 3.0 V. The improvement of the short-channel effect, the current voltage characteristics, and the power-delay product are obtained by the scaling of the DSA MOS transistor.