Short channel erase in n-channel Si-gate MNOS EEPROM transistors

A unipolar method of erasing MNOS EEPROM transistors with short channel lengths by reverse-biasing of source and drain with gate and substrate grounded is described for n-channel Si-gate transistors. With pulse conditions kept constant, the threshold voltage shift caused by short channel erase (SCE) depends strongly on channel length and nitride thickness of the transistors. At effective channel lengths < 0.4 μm, SCE voltages V_SCE < 20 V are sufficient to cause a shift in the threshold voltage comparable to the value obtained with 25 V pulses using the conventional erase method and both voltage polarities.SCE voltage measurements at varied temperatures show that the results are in agreement with the model conception of the avalanche punch-through erase (APTE) mode. The retention data have been found regardless of the SCE treatment. Endurance has been investigated by multiple cycling of MNOS transistors using up to 10⁷ pulses of 25 V, 100 μs. The effective window width did not change, but the transconductance was found to decrease slightly with cycle number.     

Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress

Device degradation modelling is more and more important for reliable circuit design. On MOSFET, the threshold voltage drift in time can lead to circuit performance degradation. In this study, V_T shift due to Hot Carrier Injection stress is accelerated on small width devices. V_T matching is also degraded during stress as a function of V_T deterioration. This width dependence allows explaining gate voltage matching behavior in the sub-threshold area used in low power analog applications.     

Characterization of scaled MANOS nonvolatile semiconductor memory (NVSM) devices

We have modeled and characterized scaled Metal–Al₂O₃–Nitride–Oxide–Silicon (MANOS) nonvolatile semiconductor memory (NVSM) devices. The MANOS NVSM transistors are fabricated with a high-K (K_A = 9) blocking insulator of ALD deposited Al₂O₃ (8 nm), a LPCVD silicon nitride film (8 nm) for charge-storage, and a thermally grown tunneling oxide (2.2 nm). A low voltage program (+8 V, 30 μs) and erase (?8 V, 100 ms) provides an initial memory window of 2.7 V and a 1.4 V window at 10 years for an extracted nitride trap density of 6 × 10¹⁸ traps/cm³ eV. The devices show excellent endurance with no memory window degradation to 10⁶ write/erase cycles. We have developed a pulse response model of write/erase operations for SONOS-type NVSMs. In this model, we consider the major charge transport mechanisms are band-to-band tunneling and/or trap-assisted tunneling. Electron injection from the inversion layer is treated as the dominant carrier injection for the write operation, while hole injection from the substrate and electron injection from the gate electrode are employed in the erase operation. Meanwhile, electron back tunneling is needed to explain the erase slope of the MANOS devices at low erase voltage operation. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data. In addition, we apply this model to advanced commercial TANOS devices.     

A new definition of threshold voltage in Tunnel FETs

This work reports on the physical definition and extraction of threshold voltage in Tunnel FETs (field effect transistors) based on numerical simulation data. It is shown that the Tunnel FET has the outstanding property of having two threshold voltages: one in terms of gate voltage, V_TG, and one in terms of drain voltage, V_TD. These threshold voltages can be physically defined based on the transition between a quasi-exponential dependence, and a linear dependence of the drain current on V_GS or V_DS, and by extension, on the saturation of the tunneling energy barrier width narrowing. The extractions of V_TG and V_TD are performed based on the transconductance change method in the double gate Tunnel FET with a high-k dielectric, and a systematic comparison with the constant current method is reported. The effect of gate length scaling on these Tunnel FETs’ threshold voltages, as well as the dependence of V_TG on applied drain voltage and V_TD on applied gate voltage, are investigated.     

Accurate negative bias temperature instability lifetime prediction based on hole injection

Negative bias temperature instability (NBTI) lifetime prediction of thin gate insulator films based on hole injection without gate voltage acceleration is described and lifetime comparison between SiO₂ film and SiON film is made based on the prediction method. The acceleration parameters are most important for the accurate lifetime prediction. The proposed acceleration parameter is not the applied voltage to the gate insulator film and the temperature but quantity of the hole injection to the gate insulator film that directly relates with the quantity of holes in the inversion layer. The degradation mechanism under the excessive voltage and excessive temperature stresses are different from that in the operation conditions. Using the hole injection method, the NBTI lifetime of SiON is less than that of SiO₂. This result agrees with the reported results measured by conventional high gate fields and temperatures. By the introduction of effective stress time (=Q_hole/J_inj0), accurate lifetime prediction in terms of the V_th shift is realized, and by analyzing of relationship between I_D reduction and V_th shift, accurate lifetime prediction in terms of the I_D reduction and the degradation prediction in the circuit level are realized. These results are essential for the accurate NBTI lifetime prediction for further more integrated LSI such as very thin gate insulator films around 1 nm.     

Drain voltage limitations of MOS transistors

A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage V_PT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, V_BD, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that V_PT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. V_BD, however, decreases as the channel length, oxide thickness and diffusion depth decrease.Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.     

A modified model for Si/SiGe MOS-gate delta-doped HEMTs

An analytical model for threshold voltage (V_th) and minimum gate voltage (V_tl) of Si/SiGe MOS-gate delta-doped HEMT is presented in this letter. The model is valid for any width of the delta-doped layer and any distance of the layer from the Si/SiO₂ interface. Using the model, V_th and V_tl of a Si/SiGe MOS-gate delta-doped HEMT of known dimensions are calculated. To investigate the effect of variation of the width of the delta-doped layer, the threshold voltage and the minimum gate voltage have been plotted against the width. Medici™ simulation have been performed on the same device to evaluate V_th and V_tl for different delta-doped layer widths. The simulation results are in good agreement with the results found using the analytical model.     

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

On threshold and flat-band voltages for MOS devices with polysilicon gate and nonuniformly doped substrate

Expressions for the flat-band voltage V_FB and threshold voltage V_T for MOS devices with polysilicon gate and nonuniformly doped substrate are given. The role of metal-semiconductor contacts and the assumptions involved in the analysis are discussed. Both V_FB and V_T have three extra terms over the conventional expressions, two terms result from nonuniform doping and one is due to a voltage drop in the gate produced by space charge. Contrasts are made to devices with metal gates and uniformly doped substrates. The commonly used expression for mobile channel charge in terms of gate voltage is clarified.     

FLOTOXEEPROM擦写过程中隧道氧化层陷阱俘获电荷的研究

本文首先从理论上分析FLOTOX EEPROM隧道氧化层中陷阱俘获电荷对注入电场和存储管阈值电压的影响,然后给出了在不同擦写条件下FLOTOX EEPROM存储管的阈值电压与擦写周期关系的实验结果,接着分析了在反复擦写过程中陷阱俘获电荷的产生现象.对于低的擦写电压,擦除阈值减少,在隧道氧化层中产生了负的陷阱俘获电荷;对于高的擦写电压,擦除阈值增加,产生了正陷阱俘获电荷.这一结果与SiO₂中电荷的俘获——解俘获动态模型相吻合.     

600V HVIC高噪声抑制电平移位电路

A novel level shift circuit featuring with high dV/dt noise immunity and improved negative V_S capacity is proposed in this paper.Compared with the conventional structure,the proposed circuit adopting two cross-coupled PMOS transistors realizes the selective filtering ability by exploiting the path which filters out the noise introduced by the dV/dt.In addition,a differential noise cancellation circuit is proposed to enhance the noise immunity further.Meanwhile,the negative V_S capacity is improved by unifying the detected reference voltage and the logic block’s threshold voltage.A high voltage half bridge gate drive IC adopting the presented structure is experimentally realized by using a usual 600 V BCD process and achieves the stable operation up to 65 V/ns of the dV/dt characteristics.     

A write-operation model for the FCAT-II-A 50 NS at 15 V alterable nonvolatile memory

An operational model is described for FCAT-II (Floating Si-gate Channel Corner AvalancheTransition-II) nonvolatile memory devices or that can perform high speed write 1 and write 0 operations with 15 V pulses of less than 50 ns duration. The novel write-enable threshold phenomenon in the high-speed write-1 characteristics is quantitatively analyzed by introducing an equivalent circuit model in which the resistive floating gate over the oxide steps plays an important role as a reverse-biased p-n junction. The analytical expression for the write-enable threshold, V_WE, has quantitatively good agreement with experimental results.     

An optimization technique for parameter extraction of ultra-deep submicron LDD MOSFET’s

An optimization technique to determine the threshold voltages V_th is proposed for meaningful parameter extractions of ultra-deep submicron LDD MOSFETs. The novel technique, coupled with some traditional V_th determination techniques, are implemented in several existing extraction methods to extract the parasitic series resistance R_ds, the effective channel length L_eff , and the effective mobility μ_eff of ultra-thin gate oxide LDD MOSFETs on 90 nm CMOS technology. A comparison among these extractions demonstrates that the technique of V_th optimization maintains the accuracy of extractions, avoids the intentional choice of the gate voltage range, and eliminates the impact of close interdependence among these parameters on the meaningful extraction, especially at high gate voltage range. Furthermore, the novel technique can reduce the extraction variance of different extraction methods, hence, suitable for application in device compact model.     

Effect of the work function of gate electrode on hysteresis characteristics of organic thin-film transistors with Ta2O5/polymer as gate insulator

Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta₂O₅) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode. The hysteresis characteristics were studied by the repetitive gate voltage sweep of OTFTs, and capacitance–voltage (C–V) and trap loss-voltage (G_p/ω?V) measurements of metal–insulator–semiconductor (MIS) devices. It is proved that the hysteresis characteristics of OTFTs are relative to the electron injection from gate metal to Ta₂O₅ insulator. The electron barrier height between gate metal and Ta₂O₅ is enhanced by using Au as gate electrode, and then the electron injection from gate metal to Ta₂O₅ is reduced. Finally, low hysteresis OTFTs were fabricated using Au as gate electrode.     

Atmos—An electrically reprogrammable read-only memory device

An adjustable threshold MOS (Atmos) transistor is described that can be used as an electrically reprogrammable read-only memory by changing the charge content of a floating polysilicon gate. This floating gate is charged negatively (write) by means of a nonavalanche mechanism and charged positively (erase) by the avalanche breakdown of source or drain junction and subsequent hole injection into the oxide. The write time is between 10 and 100 ms, the erase time on the order of 1 s. The charge retention of the floating gate is about 90 percent after storage for 1000 h at 125°C.     

FCAT-II: A 50 ns/15 V alterable nonvolatile memory device—Part I: Experimental

A new structure for an n-channel Floating Si-gate Channel Corner Avalanche Transition nonvolatile memory device (FCAT-II) and its novel write-erase characteristics are described. The new structure is a modification of the previously reported FCAT (FCAT-I) memory device. The key improvement is better coupling between the floating gate and the control gate. This makes Fowler-Nordheim tunneling the major electron injection mechanism in the floating gate. The p⁺-p junctions placed outside the channel area are self-aligned with the floating gate and have an important role in crowding and raising the electron injection field. The device can operate in both write and erase modes at high-speed (≥ 50 ns) and low-voltage (≤15 V) conditions using only positive pulses. Another useful feature is the saturation of the high level threshold voltage independent of write pulse width greater than 50 ns. Reliability of this device is as good as that of FCAT-I.     

Vertical silicon-on-nothing FET: Threshold voltage calculation using compact capacitance model

The threshold voltage (V_th) model of the novel vertical fully-depleted silicon-on-nothing FET (VFD SONFET) structure is extracted from the compact capacitance equivalent circuit. Due to the absence of the transistor substrate in the VFD SONFET, the channel region is coupled to the source and drain through the buried oxide. Electrostatically, the VFD SONFET resembles the SOI device with thick buried oxide and recessed source/drain, and the developed model can also be applied to these structures. This property is modeled by two-dimensional buried oxide capacitance (C_BOX), which competes for the inversion charge with gate oxide capacitance (C_GOX). Therefore, the V_th is primarily influenced by the ratio of buried and gate oxide capacitances, with the negligible effect of the silicon body equivalent capacitance and the silicon body charge. The relative impact of C_BOX increases with the down-scaling of the effective channel length. In the VFD SONFET structure, the inversion channel can be formed at the back interface of the channel region, due to its coupling to the n⁺ source and drain regions. However, it is shown by the model that the V_th value is minimally changed in this case, due to a small potential change in the silicon channel. The model accurately predicts V_th in comparison to physical simulations, especially in the long channel region, whereas accuracy drops for shorter channels. The maximum absolute deviation is below 50 mV for the channel lengths above 30 nm.     

Highly-sensitive solution-processed 2,8-difluoro-5,11-bis(triethylsilylethynyl) anthradithiophene (diF-TESADT) phototransistors for optical sensing applications

A highly-sensitive organic phototransistor, based on solution-processed 2,8-difluoro-5,11-bis(triethylsilylethynyl) anthradithiophene (diF-TESADT) was fabricated and investigated for an optical sensing element. The phototransistor based on thin crystalline grains of diF-TESADT exhibited a significant threshold voltage (V_TH) shift under a white light illumination in which the response time was estimated to be <0.5 s and a current modulation greater than 10⁶. It was found that the V_TH shift can be further enlarged by an additional gate bias, achieving very high light responsivity >10³ A/W at 0.17 mW/cm² and I_PH/I_DARK ratio higher than 10⁶. Also, by applying an erase gate bias, fast recovering of V_TH to the initial position was possible. This phenomenon can be ascribed to the trapping and de-trapping of photo-generated carriers at the organic channel/dielectric interface, while the amount of trapped carriers can be also modulated simultaneously by the gate bias. This investigation identifies that the solution-processed diF-TESADT phototransistors can be used for large-area and low-cost optical sensors and memory applications. In particular, it can be claimed that performance improvement by a gate bias represents a universal method applicable to the organic phototransistors.     

A new write/erase method to improve the read disturbcharacteristics based on the decay phenomena of stress leakage currentfor flash memories

This paper describes a new write/erase method for flash memory to improve the read disturb characteristics by means of drastically reducing the stress leakage current in the tunnel oxide. This new write/erase operation method is based on the newly discovered three decay characteristics of the stress leakage current. The features of the proposed write/erase method are as follows: 1) the polarity of the additional pulse after applying write/erase pulse is the same as that of the control gate voltage in the read operation; 2) the voltage of the additional pulse is higher than that of a control gate in a read operation, and lower than that of a control gate in a write operation; and 3) an additional pulse is applied to the control gate just after a completion of the write/erase operation. With the proposed write/erase method, the degradation of the read disturb life time after 10⁶ write/erase cycles can be drastically reduced by 50% in comparison with the conventional bipolarity write/erase method used for NAND type flash memory. Furthermore, the degradation can he drastically reduced by 90% in comparison with the conventional unipolarity write/erase method fur NOR-, AND-, and DINOR-type flash memory. This proposed write/erase operation method has superior potential for applications to 256 Mb flash memories and beyond     

Dual-electron-injector-structure electrically alterable read-only-memory modeling studies

The threshold voltage shift of various dual-electron-injector structures (DEIS's) which are composed of chemically vapor-deposited (CVD) stacks of Si-rich SiO2, SiO2, and Si-rich SiO2incorporated into floating polycrystalline-silicon-gate electrically alterable read-only memories (EAROM's) has been studied as a function of write/erase voltages, write/erase times, and the initial charge state of the floating poly-Si gate and compared, to a simple physical model for a variety of different device structures. This model depends on the interface limited (Si-rich-SiO2-SiO2interfaces) enhanced current injection observed for the dual-electron-injector stacks at moderate gate voltages for both voltage polarities, the changing electric fields in the SiO2layers as the floating polycrystalline silicon gate electrode is charged or discharged, and the voltage-dependent capacitance of the dual-electron-injector stack. Good agreement is observed between the experimental data and this model. This model will be the starting point in designing more complicated device arrays for nonvolatile memory applications.