Switching characteristics of polysilicon MISS devices

Experimental results on MISS devices are reported. The insulating layer was obtained by means of electron gun evaporation of undoped polycrystalline silicon. A model taking into account the specific conduction mechanisms in the semi-insulating polysilicon layer has been developed. This model explains the experimental I-V characteristics and gives rise to a switching condition relation similar to that of p-n-p-n devices.     

A power SIPOS MISS device

Power metal-insulator-silicon-switch (MISS) devices fabricated using semi-insulating polysilicon (SIPOS) for the insulator layer are discussed. The SIPOS MISS devices have an active area of 4.5 mm² and can carry in excess of 8 A. The typical switching voltage of these devices is 20 to 25 V with a negative temperature coefficient. They have a typical switching time of 200 ns and a very fast turn-off time. No degradation in device performance is observed after high current pulsing. Power SIPOS MISS devices offer an alternative to conventional four-layer switching devices, yielding faster switching characteristics while maintaining process compatibility     

The metal-insulator-semiconductor-switch (MISS) device using thermal nitride film as the tunneling insulator

Silicon thermal nitride films grown by using direct thermal nitridation of silicon have been used as a tunneling insulator in the metal-insulator-semiconductor-switch (MISS) device. This paper has shown that better uniformity and controllability of the MISS characteristics can be easily obtained by using thermal nitride film as a tunneling insulator when compared to those using conventional thermal oxide film. The superior merits of using silicon thermal nitride film are mainly due to the fact that direct thermal nitridation of silicon in ammonia gas exhibits much lower growth rate and unique self-limiting growth. Moreover, the higher structure density of the as-grown thermal nitride film may provide higher endurance for the MISS device in integrated-circuit applications. In addition, the MISS devices operated at lower voltage (< 5 V) have been fabricated and their characteristics are discussed.     

Switching behaviour of MISS diodes

A physical picture of the switching behaviour of MISS diodes is presented considering three phases of the turn-on process: a capacitive current rise time, an inversion charge delay time and a feedback regeneration time. Approximate calculations are derived based on the outlined physical picture and compared to the experimental results obtained in pulse experiments with polysilicon MISS diodes. A dynamic current-voltage characteristic is also presented which differs from the known static one.     

Process and performance comparison of an 8K × 8-bit SRAM in three stacked CMOS technologies

Using self-aligned and non-self-aligned stacked CMOS technologies experimental 8K × 8-bit static random-access memories (SRAM'S) have been fabricated. Hydrogen passivation has been used to improve the performance of polysilicon devices. An 8K × 8-bit SRAM using non-self-aligned memory cells and employing a CW argon laser to anneal the second (active) polysilicon layer has also been fabricated. The fabrication methods and performances of all three SRAM's have been compared.     

High-gain bipolar transistors with polysilicon tunnel junction emitter contacts

Experimental measurements of the dc gain as a function of temperature and of emitter-base and collector-base current-voltage characteristics for bipolar transistors with polysilicon contacts to the emitter are reported, dc gains as high as 2000 have been measured in devices for which a thin insulating layer was encouraged to grow between the monocrystalline silicon emitter and the polycrystalline silicon contact layer. This gain is 20 times larger than that for devices in which the insulating film growth was inhibited. It is suggested that, for these particular devices, the polysilicon layer contributes to a contact which is very similar to that of a metal-insulator-semiconductor tunnel junction contact. A model based on this hypothesis is developed and shown to give a good fit to all the experimental data.     

A simulation study to evaluate the feasibility of midgap workfunction metal gates in 25 nm bulk CMOS

The performance of 25 nm metallurgical channel length bulk MOSFETs with midgap workfunction metal gates has been compared with conventional polysilicon gates and bandedge workfunction metal gates. Device design using pocket halo implants was implemented to achieve the required off-state leakage specification. Highly accurate, full device simulations have been performed with a linear chain of inverters taking quantum effects into consideration. Drain induced barrier lowering (DIBL) was used as an indicator of short channel effects, and the stage delay of a linear chain of inverters and the on state drive current (I/sub on/) have been identified as metrics for performance. Compared to bandedge metal gates, midgap gates suffer from lower drive currents for both NMOS and PMOS devices. On the other hand, midgap devices were comparable in their performance to N/sup +/ polysilicon gated devices and exceeded that of P/sup +/ polysilicon devices. This high performance was attributed to a lack of poly depletion in midgap metal devices and a higher degree of DIBL which resulted in a lower V/sub t/ under high drain bias providing high drive current. Conclusions have been drawn on the feasibility of using midgap metal gates to simplify process integration in future generation CMOS devices.     

On-chip ESD protection design by using polysilicon diodes in CMOSprocess

A novel on-chip electrostatic discharge (ESD) protection design by using polysilicon diodes as the ESD clamp devices in CMOS process is proposed in this paper. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimizing the polysilicon diodes for both on-chip ESD protection design and the application requirements of the smart-card ICs. The secondary breakdown current (It2) of the polysilicon diodes under the forward- and reverse-bias conditions has been measured by the transmission-line-puIse (TLP) generator to investigate its ESD robustness. Moreover, by adding an efficient VDD-to-VSS clamp circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilicon diodes as the ESD clamp devices has been successfully improved from the original ~300 V to become ⩾3 kV. This design has been practically applied in a mass-production smart-card IC     

Influence of the polysilicon doping on the electrical quality of thin oxides: a confrontation between vertical and horizontal furnaces

In this work, the influence of polysilicon doping on thin oxides (thickness equal or below 10 nm) quality and reliability (thickness equal or below 10 nm) in MOS capacitors with polysilicon gate is evaluated. By observing the polysilicon deposed in vertical and horizontal furnaces, a higher degradation in the oxide–silicon interface at high doping concentration has been found. In the case of vertical furnaces, a more evident charge trapping in the constant current stress (CCS) V(t) curves and Qbd (ERCS) degradation have also been noticed. Resistivity measurements at different concentrations show a saturation effect just in correspondence of the oxide degradation. From a morphological point of view, the poly deposited in vertical furnaces consists of grains which are larger than the ones found in horizontal furnace polysilicon and contains lower microdefectivity. Starting from these observations a model explaining the polysilicon morphology role in the oxide reliability can be proposed. According to it, the degradation of the interface is caused by the phosphorus coming from the “in situ” doped polysilicon. The hypothesis is that, at high concentrations and in presence of very large polysilicon grains, phosphorous cannot segregate at the interfaces among the polysilicon grains and, moving through the thin oxide, damages the silicon interface. This model has been confirmed by electrical, AFM and TEM analysis and all the collected data have been related to the finished devices performances (yield and reliability of CMOS flash memories, 0.25 μm technology and below).     

ESD robustness of thin-film devices with different layout structures in LTPS technology

The electrostatic discharge (ESD) robustness of different thin-film devices, including three diodes and two thin-film transistors (TFTs) in low-temperature polysilicon (LTPS) technology, is investigated. By using the transmission line pulse generator (TLPG), the high-current characteristics and the secondary breakdown current (It2) of these thin-film devices are observed. The experimental results with different parameters and layout structures of these LTPS thin-film devices have been evaluated for optimizing ESD protection design for liquid crystal display (LCD) panel.     

Information Content-Based Sensor Selection and Transmission Power Adjustment for Collaborative Target Tracking

For target tracking applications, wireless sensor nodes provide accurate information since they can be deployed and operated near the phenomenon. These sensing devices have the opportunity of collaboration among themselves to improve the target localization and tracking accuracies. An energy-efficient collaborative target tracking paradigm is developed for wireless sensor networks (WSNs). A mutual-information-based sensor selection (MISS) algorithm is adopted for participation in the fusion process. MISS allows the sensor nodes with the highest mutual information about the target state to transmit data so that the energy consumption is reduced while the desired target position estimation accuracy is met. In addition, a novel approach to energy savings in WSNs is devised in the information-controlled transmission power (ICTP) adjustment, where nodes with more information use higher transmission powers than those that are less informative to share their target state information with the neighboring nodes. Simulations demonstrate the performance gains offered by MISS and ICTP in terms of power consumption and target localization accuracy.     

Physics, technology, and modeling of polysilicon emitter contacts for VLSI bipolar transistors

The physics of minority-carrier injection into polysilicon-contacted emitters has been studied through a series of experiments correlating the base current of the transistor to the structure of the polysilicon/single-crystal silicon interface. Most of the relevant material and processing parameters have been examined. In addition, a novel approach has been taken in the modeling of transport in these emitters to quantify the minority-carrier blocking properties of the polysilicon contacts. Experimental results show that extremely low values of base current can be obtained for devices etched in HF prior to the polysilicon deposition, i.e., devices with only a remnant "native" oxide layer at the polysilicon/single-crystal silicon interface. For these devices, the base current is mainly determined by the recombination and blocking of minority carriers at the polysilicon/monosilicon interface. A number of competing mechanisms exist in several domains of doping, temperature, and time which influence the properties of this interface. One of these mechanisms is the blocking of minority carriers by the native oxide layer itself. The uniformity and, consequently, the blocking characteristics of this layer were found to be strongly affected by the polysilicon doping level and thermal treatment.     

Novel self-aligned polysilicon-gate MOSFETs with polysilicon source and drain

A novel self-aligned technique is described for self-aligning a polysilicon gate in devices with polysilicon source and drain regions. The technique is demonstrated for two types of polysilicon source and drain devices. In one type of device, the polysilicon serves as the source of dopant for diffused source and drain junctions. In the second type, the polysilicon, together with an underlying interfacial oxide, forms a tunneling CIS (conductor-thin insulator-semiconductor) structure. The characteristics of devices of both types fabricated under almost identical conditions using the new self-alignment technique are compared.     

L波段150W宽带硅脉冲功率晶体管

设计了一种称之为多晶硅覆盖树技状结构的双极型微波功率晶体管。该器件采用掺砷多晶硅发射极，同时具备有覆盖和树枝状两种图形结构的优点。器件引入扩散电阻和分布式多晶硅电阻组合而成的发射极复合镇流电阻，实现对发射极电流二次镇流，器件表现出良好的微波性能和高的可靠性。经内匹配，在L波段脉冲输出大于100W（36V），脉宽150μs，工作比10％，增益大于7．5dB，效率大于45％，器件最大输出达150W（42V）。     

Evaluation of MUMPS polysilicon structures for thermal flow sensors

The air flow measurement has been studied for its application in many fields. Among flow sensors, those operated under a thermal principle have occupied an important position. The application of micro-electro mechanical systems (MEMS) technologies for designing such devices will allow reducing its size, response time and to increase the sensitivity.In the community of MEMS’ designers it is well established a multi-user service for prototyping named multi-user MEMS processes (MUMPS). It is a general purpose surface micromachining process which employs polysilicon as structural material and silicon oxide as sacrificial layer. There are no reported, to the best of our knowledge, flow sensors developed using this technology.In this work the linear and quadratic temperature coefficients of polysilicon resistors are experimentally determined in anchored, suspended and stacked microstructures fabricated with this process to study their suitability for flow and temperature sensors. The thermal resistance of the three structures is also calculated, determining that suspended plates characteristics indicate their suitability for constant temperature anemometers.     

Control of boron diffusion in polysilicon for constructing overlapping polysilicon gate charge-coupled devices

The diffusion coefficient of boron having values significantly different in silicon and silicon dioxide has been used to control the doping of boron impurity in intrinsic polysilicon deposited over the gate oxide. The method reduces the possibility of doping gate oxide while diffusing boron in polysilicon. Using the method, silicon gate p-MOSFETS and twenty bit photo-sensor, four phase, double overlapping polysilicon gate surface channel charge-coupled devices have been constructed with a transfer efficiency of 0.9990. The measured values of the threshold voltage of MOSFETS are in close agreement with their corresponding calculated values.     

Characterization of phosphorus and boron heavily doped LPCVDpolysilicon films in the temperature range 293-373 K

In this paper, thermal properties of phosphorus and boron-doped low pressure chemical vapor deposition (LPCVD) polysilicon layers with regard to sensor applications are presented. Thermoelectric coefficient and relative resistance variations of polysilicon are investigated within the temperature range of 293-373 K. Test structures and characterization benches have been developed to obtain measurements with precision of 5%. Ion implantation has been experimented to achieve low electrical resistivities and high Seebeck coefficients. It can be seen that the temperature coefficient of resistance of doped polysilicon is negative, approaches zero, or positive depending on the doping concentration. These results are, to our knowledge, the first reported for such dopant concentrations and are important for design and optimization of high sensitivity thermal sensors using n- and p-doped-LPCVD polysilicon thermopile     

Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

An As-P double-diffused lightly doped drain (LDD) device has been designed and fabricated with a self-aligned titanium disilicide process. The device design was aided by using an analytical one-dimensional model, and analytic results agree well with experimental data on the avalanche breakdown voltage gain and the ratio of substrate current to source current. Threshold voltage and subthreshold characteristics of this device do not deviate from those of a conventional device without LDD and silicide. The drain avalanche breakdown voltage of the LDD device is higher by 2.5 V over the conventional device. Transconductance degradation was observed for the LDD devices due to the inherently high source-drain series resistance of the LDD structure. Substrate current is reduced and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain diffusion and the polysilicon gate to 3 Ω/sq compared with 150 Ω/sq of the unsilicided counterparts. It is also found that larger polysilicon grain size increases the sheet resistance of the silicide gate due to discontinuous titanium disilicide formation on top of polysilicon.     

Anomalous off-current mechanisms in N-channel poly-Si thin film transistors

The anomalous off-current (I_off) in polysilicon thin film transistors (polysilicon TFTs) is one of the major problems preventing a wide use of these devices in active matrix liquid crystal displays. While previous investigations have focused on the temperature range above 300 K, in this study we have investigated the behaviour of I_off over a wide range of temperatures, namely 180–400 K. The data have been analysed by combining 2D simulations and existing analytic models. By this approach we have identified a pure trap-to-band tunnelling mechanism in polysilicon TFTs and deduced, by a simple procedure, the physical constants. The temperature and bias dependence of the off-current has been explained quantitatively in terms of phonon-assisted tunnelling. The number of generating centres, the dominant trap energy and the thermal capture cross section are deduced from this analysis.     

Comparison of experimental and theoretical results on polysilicon emitter bipolar transistors

Two types of polysilicon emitter transistors have been fabricated using identical processing except for the surface treatment prior to polysilicon deposition. The first type was given a dip etch in buffered hydrofluoric acid, which was intended to remove any interfacial oxide, while the second type was given an RCA clean, which was intended to grow an interfacial oxide of known thickness. Detailed electrical measurements have been made on these devices including the temperature dependence of the gain over a wide temperature range. The transistors given an RCA clean have gains approximately five times higher than those given an HF etch. In addition, the temperature dependence of the gain is different for the two types, with the HF devices exhibiting a much stronger dependence at high temperatures than the RCA devices. A detailed comparison is made with the theory and it is shown that the characteristics of the HF devices can largely be explained using a transport theory, while those of the RCA devices can be fully explained using a modified tunneling theory.