Substrate current in short n-channel MOS transistors

Tho substrain current against gate voltage characteristics or relatively short n-channel MOS transistors were examined for various substrate and drain voltages, channel length and surface doping conditions : namely without implantation, implantation for threshold voltage adjustment and implantation for depletion mode device types A, B and C, respectively. The substrate current may increase or decrease when increasing the aubstrate voltage magnitude duo to the fact that the drain current decreases and the multiplication factor increases with the substrate bias. The substrate current increases when decreasing the channel length. It increases for the devices of type B, but is lower for type C. These experimental results were qualitatively explained by using published models in which the substrate current is caused by low-level impact ionization within the pinched-off region. A simple model in which the ionization coefficient and the field derivative with respect to x wore assumed to be power-law field-dependent correctly predicts the behaviour of the substrate current.     

Noise in phosphorus-implanted buried channel MOS transistors

Noise measurements on phosphorus-implanted buried channel MOS transistors are reported. The data are interpreted as two superimposed generation-recombination (g – r) spectra with different time constants plus a white spectrum due to thermal-like noise of the conducting channel.     

Low-noise operation of buried channel MOS transistors

Results are presented which show that extremely low-noise performance is possible in buried n-channel transistors. By careful choice of operating point, low-noise operation with useful gain is possible. The use of these devices as circuit elements is discussed.     

Direct capacitance measurements of small geometry MOS transistors

Methods for measuring the intrinsic capacitances of small geometry MOS transistors are described. The influence of short- and narrow-channel effects on the capacitance characteristics of MOS transistors is evaluated. The results are compared with long-channel devices. It is shown that the presented capacitance methods can be used to study the physics of short-channel transistors.     

Equivalent input spectrum and drain current spectrum for 1/ƒ noise in short channel MOS transistors

Flicker noise in MOS transistors can be evaluated by measuring the spectrum S_ID of the drain current fluctuation or the spectrum Sve of an equivalent gate fluctuation. We show here that experimental variations of are in good agreement with g_m² by considering a model of the transconductance g_m which takes into account the variations of the channel carriers mobility with the surface electric field. The model agrees with the experimental results obtained on short channel MOS transistors which exhibit large variations of mobility with the gate voltage. The validity of physical interpretations of noise data on MOS transistors is examined.     

A reliable approach to charge-pumping measurements in MOS transistors

A new and accurate approach to charge-pumping measurements for the determination of the Si-SiO2interface state density directly on MOS transistors is presented. By a careful analysis of the different processes of emission of electrons towards the conduction band and of holes towards the valence band, depending on the charge state of the interface, all the previously ill-understood phenomena can be explained and the deviations from the simple charge-pumping theory can be accounted for. The presence of a geometric component in some transistor configurations is illustrated and the influence of trapping time constants is discussed. Furthermore, based on this insight, a new technique is developed for the determination of the energy distribution of interface states in small-area transistors, without requiring the knowledge of the surface potential dependence on gate voltage.     

Low frequency noise measurements on silicon-on-sapphire (SOS) MOS transistors

Measurements of the equivalent input noise are performed on P-channel silicon-on-saphire, metal-oxide-semiconductor (SOSMOS) transistors as a function of the silicon layer bias voltage with respect to the source. Devices are operated in the ohmic region of the characteristics so that the results are easier to analyse. The results show a high degree of dispersion in the noise characteristics for the different tested devices all originated from the same silicon on sapphire wafer. We conclude that a dispersion of the silicon-sapphire interface properties, such as SRH centers density or fixed positive charge, exists on the wafer. From one specific device, we calculate a fixed positive silicon-sapphire interface charge (about 4 × 10¹¹ cm^?2) and a high density (about 5 × 10¹¹ cm^?2) SRH centers localized near the silicon-sapphire interface.     

Electron dynamics in short channel field-effect transistors

The dynamics of electrons between the source and drain of a microwave field-effect transistor (FET) have been studied using a Monte Carlo method. The spatial dependence as well as the time dependence of the average electron velocity is presented. It is shown that in silicon the relaxation time is short enough not to influence the figure of merit of the transistor. However, in direct gap polar semiconductors (e.g., GaAs), the electrons can have a velocity well above their saturation value for an appreciable length of time and, consequently, over a distance nonnegligible compared to the length of the active region of a high frequency FET. This could improve the figure of merit of the FET.     

关于短沟道双栅无结型晶体管的仿真研究

We study the characteristics of short channel double-gate(DG) junctionless(JL) FETs by device simulation. OutputⅠ-Ⅴcharacteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed.Distributions of electron concentration,electric field and potential in the body channel region are also analyzed.Comparisons with conventional inversion-mode(IM) FETs,which can demonstrate the advantages of JL FETs,have also been performed.     

Determination of spatial surface state density distribution in MOS and SIMOS transistors after channel hot electron injection

The charge pumping technique has been adapted for the determination of the spatial distribution of the interface state density in the channel region of short channel MOS or SIMOS transistors. This spatial distribution is shown to be modified by channel hot electron injection and provides information on the location and width of the injection region.     

Errors in threshold-voltage measurements of MOS transistors for dopant-profile determinations

The dopant and trap density profiles in MOSFETs can be deduced from the static and transient variations of V_T caused by changes in V_BS. This letter reports a study of errors in V_T measurements by three different methods. Relatively small errors in V_T could cause serious inaccuracies in dopant profiles. It is found that the major source of errors is the non-constancy of the surface mobility and that errors in V_T measured by a “constant V_GS?V_DS method” cannot be eliminated easily. However, with properly chosen V_GS?V_T or I_D, a “constant I_D?V_DS method” can provide almost error-free measurements of V_T. The theoretical predictions agree with experiments.     

Bipolar mechanisms present in short channel SOI-MOSFET transistors

The set of physical mechanisms present in the body of SOI MOS transistors has been presented. Selected bipolar aspects of physical phenomena usually oversimplified in existing SOI MOS models have been analyzed. The action of parasitic bipolar transistor present in the body of SOI MOS transistor is one of them and seems to become especially important as transistor channel dimensions are reduced.     

Large- and small-signal channel transit time delays in long-channel MOS transistors

Turn-on and turn-off delay times (intrinsic channel transit times) of long-channel MOST's are studied for both large-and small-signal inputs. By developing large-signal dynamic equations in normalized form it is evident that the normalized channel current and voltage distributions are unique and independent of device parameters and applied voltages. Channel transit time delays for both large and small signal are found to be given by a simple analytical expression containing a constant, undefined for large signal but defined explicitly for small signal. Values for the constant are found for large- signal operation in several modes by computer simulation representing the channel as a series of cascaded CCD elements. Those for small signal are found by representing the channel as anRCtransmission line. With the values of the constant determined, the simple analytical expression is shown to accurately predict channel transit time delays regardless of device type, channel length, width, substrate doping, crystal orientation, or effective mobility. It is concluded that the data presented can be used in designing delay lines or low-pass filters employing long-channel devices.     

页岩孔隙结构扫描电镜分析方法研究

页岩气是储集在富含有机质的页岩(泥岩)中的天然气,已经成为重要的非常规天然气资源.页岩气以吸附或游离状态存在于微小孔隙中,这些微孔隙、微裂隙既是页岩气重要的储存空间也是流通通道.页岩中的孔隙有微米级别,也有纳米级别,微米级孔隙采用新鲜断面的方法,可以用扫描电镜直接观察到,但由于新鲜断面表面粗糙,很难观察到纳米级孔隙及分布状况.用氩离子抛光的方法对样品表面进行处理,可以使样品表面变的光滑平整,使用背散射电子成像方式,有利于观察纳米级孔隙及孔隙形状、大小及分布规律等.本文还对平行层理及垂直层理两种取样方法进行了对比,两种方法相结合观察更全面,效果更好.     

Understanding wide-band MOS transistors

A quantitative understanding of MOS-transistor speed has been slow to emerge because of the absence of a commonly agreed-upon figure of merit for MOS-transistor speed and a lack of familiarity among designers with MOS-amplifier topologies. It is suggested that these problems can be addressed through the use of the unity-gain current frequency (f _T) as a figure of merit for MOS transistors, the use of f_T in the prediction of amplifier bandwidth, and a wider familiarity among designers with practical examples of MOS wideband amplifiers. The use of f_T as a figure of merit is discussed, and the achievable amplifier bandwidths are determined. Increasing the f_T of an MOS device by making the g_m larger or the C_g smaller, or both, is discussed. Wideband CMOS amplifiers are considered     

Efficiency of frequency transformation on MOS transistors with a built-in channel under intensively handicapped radioreception

An algorithm and a technique are developed for finding the maximum values of the target current components in a MOS transistor with an n-type built-in channel depending on the submicron and nanoscale topological norms for a frequency transformer in the presence of intensive noise at its input. The spectral making components of the intermediate frequency are evaluated and analyzed for the given amplitudes of the generator, signal, and handicap. The behavior of the n-MOS transistors designed according to the GPDK045 and GPDK0990 technological norms is investigated.     

Thermal stability of organic transistors with short channel length on ultrathin foils

We demonstrate an effective design for fabrication of short channel organic transistors (<3 μm channel length) on ultrathin 1 μm thick substrates that exhibit excellent thermal stability. For short channel transistors, we demonstrate durability up to 170 °C, with a theoretical cutoff frequency above 100 kHz, and stable performance in cyclic heating tests up to 120 °C. We fabricate inverter circuits to investigate their behavior upon heating and show that inverter gain can be improved by 150%. Device performance and topology changes were systematically analyzed after annealing steps to gain better understanding on the mechanism behind the performance change. This report on the thermal stability of short channel transistors on ultrathin films shows good durability at elevated temperatures and paves the way for high frequency imperceptible electronics.     

Direct writing of inkjet-printed short channel organic thin film transistors

A direct-writing fabrication process for fully inkjet-printed short-channel organic thin-film transistors (OTFTs) has been developed. Channels as narrow as 800 nm between two printed Ag electrodes were achieved by printing a special Ag ink on an SU-8 interlayer, which can be partially dissolved by the solvents used in the Ag ink. The ridge formed along the printed Ag line edges due to redistribution of the interlayer material during the drying process limits the ink spread, and separates neighboring printed lines, and is the key to defining an ultra-narrow channel for transistor fabrication. The short-channel OTFTs fabricated using this technique have demonstrated well-defined linear and saturation regimes. An extracted mobility of 0.27 cm²/Vs with an on/off ratio of 10⁵ was obtained at a driving voltage of −12 V. The excellent performance of these devices demonstrates the potential of this technique in fabrication of short-channel devices using standard printing technologies.     

Enhanced electron trapping near channel edges in NMOS transistors

Charge trapping in the gate oxide of NMOS transistors due to constant-voltage Fowler-Nordheim injection was investigated. Results from several different measurement methods consistently indicated strongly enhanced electron trapping in the gate oxide near the channel edges and in the gate oxide overlaps above drain and source, although net positive charge was observed in the bulk of the channel. The edge trapping effect could increase the electrical channel length by as much as 0.5 μm and is independent of the channel length. Possible reasons for the observed phenomena are discussed