GaAs DCFL超高速集成电路研究

直接耦合场效应逻辑（ＤＣＦＬ）具有简单的结构、良好的速度／功耗性能，是ＧａＡｓＦＥＴＬＳＩ电路中一种重要的逻辑形式。传统Ｅ／Ｄ型ＤＣＦＬ电路具有较低的成品率和较差的温度特性，本文研究了改进的Ｅ／Ｅ型ＤＣＦＬ电路。对Ｅ／Ｄ、Ｅ／Ｅ型ＤＣＦＬ电路的直流、瞬态及温度特性进行了分析、模拟和比较，Ｅ／Ｅ逻辑具有良好的高温性能。经优化设计，最后制作出单门延迟约１００ｐｓ、单门功耗约１ｍＷ的Ｅ／Ｄ和Ｅ／Ｅ型ＤＣＦＬ电路，且Ｅ／Ｅ型电路较Ｅ／Ｄ型电路具有更高的成品率。     

DVD的调制方式EFM plus（8／16调制）

ＤＶＤ的调制方式ＥＦＭｐｌｕｓ（８／１６调制）张绍高ＤＶＤ（ＤｉｇｉｔａｌＶｉｄｅｏｄｉｓｃ，数字视频光盘，或ＤｉｇｉｔａｌＶｅｒｓａｔｉｌｅＤｉｓｃ，数字通用光盘）的调制方式ＥＦＭｐｌｕｓ（８／１６调制）是在ＣＤ的ＥＦＭ（Ｅｉｇｈｔ－Ｆｏｕｒｔｅｅ...     

GaAs DCFL超高速集成电路研究

直接耦合场效应逻辑（ＤＣＦＬ）具有简单的结构、良好的速度／功耗性能，是ＧａＡｓ ＦＥＴＬＳＩ电路中一种重要的逻辑形式。传统Ｅ／Ｄ型ＤＣＦＬ电路具有较低的成品率和较差的温度特性，本文研究了改进的Ｅ／Ｅ型ＤＣＦＬ电路。对Ｅ／Ｄ、Ｅ／Ｅ型ＤＣＦＬ电路的直流、瞬态及温度特性进行了分析、模拟和比较，Ｅ／Ｅ逻辑具有良好的高温性能。经优化设计，最后制作出单门延迟的１００ｐｓ、单门功耗的１ｍＷ的Ｅ／Ｄ和Ｅ／Ｅ型Ｄ     

2英寸GaAs快速热退火技术研究

为配合２０００门ＧａＡｓ超高速门阵列及ＧａＡｓ超高速分频器等２英寸ＧａＡｓ工艺技术研究，开展了２英寸ＧａＡｓ快速热退火技术研究。做出了阈值电压为０～０．２Ｖ，跨导大于１００ｍＳ／ｍｍ的Ｅ型ＧａＡｓＭＥＳＦＥＴ和夹断电压为－０．４～－０．６Ｖ，跨导大于１００ｍＳ／ｍｍ的低阈值Ｄ型ＧａＡｓＭＥＳＦＥＴ。     

最新的通信IC

以下介绍的通信ＩＣ都是各公司１９９６年的最新产品，其品种涉及到ＰＣＳ手机、无绳电话、无线通信、卫星电视、调制解调器、ＦａｓｔＥｔｈｅｒｎｅｔ和ＡＴＭ等。＋３ＶＤＣＰＣＳ手机用分立器件和ＩＣＯｋｉ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ公司开发了一系列８００～１９００ＭＨｚＰＣＳ手机用＋３ＶＤＣ分立器件和ＩＣ。这些器件是用ＧａＡｓＭＥＳＦＥＴ技术和硅ＣＭＯＳ技术制作的。ＧａＡｓ器件包括ＫＧＦ１６０６分立ＧａＡｓ场效应管（ＦＥＴ）、ＫＧＦ１６０８分立ＧａＡｓ　ＦＥＴ和ＫＧＦ１２６２中功率ＧａＡｓ单片微波集成电路…     

THE OUTPUT OPTICAL FIELD INTENSITY DISTRIBUTION FORMED BY AN OPTICAL FIBER END

ＴＨＥＯＵＴＰＵＴＯＰＴＩＣＡＬＦＩＥＬＤＩＮＴＥＮＳＩＴＹＤＩＳＴＲＩＢＵＴＩＯＮＦＯＲＭＥＤＢＹＡＮＯＰＴＩＣＡＬＦＩＢＥＲＥＮＤ￥ＹＵＡＮＬｉ－Ｂｏ（Ｄｅｐａｒｔｍｅｎｔｏｆｐｈｙｓｉｃｓ，ＨａｒｂｉｎＥｎｇｉｎｅｅｒｉｎｇＵｎｉｖｅｒｓｉｔｙ...     

接入网的发展

本文介绍了Ｓｉｅｍｅｎｓ接入网技术，主要介绍了ＤＥＣＴｌｉｎｋ和ＣＤＭＡｌｉｎｋ无线接入，Ｆａｓｔｌｉｎｋ有源混合光纤环路。     

信息通信英语新缩略语[3]

ＥＤＦＡ(Ｅｒｂｉｕｍ -ＤｏｐｅｄＦｉｂｅｒＡｍｐｌｉｆｉｅｒ,掺铒光纤放大器 )利用光纤中掺入稀土元素饵而引起的光增益机制来实现光信号放大的光纤线路元件。ＥＤＦＦＡ(Ｅｒｂｉｕｍ -ＤｏｐｅｄＦｌｕｏｒｉｄｅＦｉｂｅｒＡｍｐｌｉｆｉｅｒ,掺铒氟化物光纤放大器 )ＥＴＥ(ＥｑｕｉｖａｌｅｎｔＴｅｌｅｐｈｏｎｅＥｒｌａｎｇｓ,等效电话占线小时呼 )一种通话计量单位。通信中话务量常以爱尔兰小时呼表示。ＥＴＳＩ(ＥｕｒｏｐｅａｎＴｅｌｅｃｏｍｍｕｎｉｃａｔｉｏｎＳｔａｎｄａｒｄｓＩｎｓｔｉｔｕｔｅ,欧洲电信标准协会 )…     

2英寸GaAs快速热退火技术研究

为配合２０００门ＧａＡｓ超高速门列及ＧａＡｓ超高速分频器等２英寸ＧａＡｓ工艺技术研究，开展了２英寸ＧａＡｓ快速热退火技术研究，做出了阈值电压为０～０．２Ｖ，跨导大于１００ｍＳ／ｍｍ的Ｅ型ＧａＡｓＭＥＳＦＥＴ和夹断电压为－０．４～－０．６Ｖ，跨导大于１００ｍＳ／ｍｍ的低阈值Ｄ型ＧａＡｓＭＥＳＦＥＴ。     

VisualFoxpro5.0与其他软件间资源共享

介绍了ＶｉｓｕａｌＦｏｘｐｒｏ提供的对象链接与嵌入技术及其应用方法,并引用了多个我详细介绍了ＶＦＰ与ＤＥＬＰＨＩ,ＥＸＣＥＬ,ＷＯＲＤ,ＶＢ等应用程序间的相互联系。     

Analysis for charged spacers in FED

Charged spacers in the field emission display (FED) are analyzed with the Monte Carlo method. The spacer is made of an insulator, which has generally a high secondary electron emission property. Under electron bombardment, the secondary electron emission induces charge on the spacer. We show that the surface of the spacer is charged positively in FED operation, which would cause an image distortion. We analyze the effect of charging on the spacer in terms of the electron density profile and luminescence profile of a dot near the spacer. Simulation results show that the image of a dot near the spacer is darker and smaller than that of a dot away from the spacer, though electrons are crowded near spacers. The results are confirmed by experiments. Finally, we suggest a way to reduce the effect of spacer charging by introducing a metal strip     

FED器件的支撑结构设计和实现

使用墙式结构作为FED器件的内的支撑，使用Algor专用力学有限元件对器件各种结构的力学特性进行了数值计算，同时对照器件的电学特性后确定了支撑墙的分布密度，安装位置和装配误差等工艺参数，并完成了现有器件条件下的工艺实现，得到理想的结果。     

场发射显示器发展动态

概述场发射显示器件的原理，结构和制作工艺及发展水平。展望ＦＥＤ的前景并介绍了国际上围绕ＦＥＤ展开的激烈竞争。     

场致发射显示器的现状与发展

通过对场致发射显示器（FED）发展现状及其应用前景进行系统的比较与分析，着重讨论了场致发射体与其阵列制备工艺以及各种关键技术的优缺点，并介绍国外著名公司的研究动态，展望FED的发展趋势。     

Feasible approach for processes integration of CMOS transistor gate/side-wall spacer patterning fabrication

As the gate length is scaling down, the spacer design for CMOS transistor becomes increasingly critical manufacturing process. In recent CMOS technologies, side-wall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present approach to overcome these fabrication limitations. The spacer patterning technology yields critical dimension variations of minimum-sized features which are much smaller than achieved by optical integrated lithography and etching processes. Generally relates to semiconductor manufacturing, and more particularly to nanotechnology fabrication feasibility for CMOS wafer process on gate spacer technology manufacture feasibility. A modified side-wall spacer patterning method was implemented for using conventional lithography and etching processing technology. Based on the systematical investigation of the effects of the various etch conditions on etching profile and their impacts on the sidewall transistor gate structure, a novel integrated process for well controlled side-wall spacer formation was developed for fabrication.     

FED up with fat tubes

Field emission displays (FED) offer the best and brightest of two display worlds: the bright picture of bulky cathode-ray tube devices and the trim flat-panel picture of liquid-crystal displays. The similarities and differences between FED and CRT are briefly mentioned. The principles of FED operation, and the fabrication of the emitter array and anode, are described     

场发射显示

本文介绍了场发射平板显示的基本结构、工作原理、场发射冷阴极的制做方法以及与其有关的若干问题，最后介绍了场发射显示的现状和发展动态。     

Influence of electrical and structural parameters on the performance of the spacers in HOPFED

The HOPping Field Emission Display （HOPFED） is a new architecture for field emission displays. The main difference between a conventional Field Emission Display （FED） device and a ItOPFED lies in the spacer structure. In a HOPFED, two dielectric plates, named hop and flu spacer, are sandwiched between the emitter and the front plate. The objective of this spacer structure is to improve the performance oF a FED substantially with notable contrast, color purity and luminance uniformity. In order to optimize the structure of the device and to make the electron spot on the screen match the requirement of the phosphor dot dimension, the influence of electrical and structural parameters of the device on the electron spot profile was studied by numerical simulation in this paper. Monte Carlo method was employed to calculate the potential distribution inside hop and flu spacers due to secondary electrons mechanism plays an important role in HOPFED. The results indicated that the potential distribution in the spacers and spot profile depended strongly on the hop voltage, anode voltage and spacer＇s layout. This study may provide a useful theoretical support for optimizing the structure in HOPFED.     

基于探针法的FED电极缺陷检测系统设计

针对FED显示屏电极的特征,提出一种FED电极缺陷检测系统,用于检测FED电极的短路和断路等缺陷。系统分为硬件和软件两部分,硬件部分由CCD摄像头初始定位和对准模块、单片机数据测试和传输模块、计算机数据接收和处理模块组成;软件部分包括单片机预处理部分的底层程序设计和计算机部分面向对象的高级程序设计。经过硬件设计安装和软件编程调试,该FED电极缺陷检测系统已经在实验中得到应用。     

Flat panel displays for portable systems

Flat panel display technologies for portable and personal information systems are reviewed. The display sub-system performance requirements, and the metrics for evaluating display technologies for portable systems are discussed. The current display technology choices for high performance portable systems are active matrix liquid crystal display (AMLCD) and field emitter display (FED). AMLCD is at the forefront at an advanced state of development, and it is already in mass production for notebook computer applications. Because of the huge market size, AMLCD technology continues to be developed at an aggressive pace to address the needs of the future portable systems. On the other hand, FED technology is not currently in mass production, but it is being developed at rapid pace; Impressive technology capabilities and demonstration displays have already been shown. This review focuses on the current status and future development trends in both the these display technologies for application to portable systems. The current status of the reflective LCDs and their future development trends are also reviewed.