共查询到19条相似文献,搜索用时 109 毫秒
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Turbo码高速译码器设计 总被引:1,自引:0,他引:1
Turbo码具有优良的纠错性能,被认为是最接近香农限的纠错码之一,并被多个通信行业标准所采用。Turbo码译码算法相比于编码算法要复杂得多,同时其采用迭代译码方式,以上2个原因使得Turbo码译码器硬件实现复杂,而且译码速度非常有限。从Turbo码高速译码器硬件实现出发,介绍Turbo码迭代译码的硬件快速实现算法以及流水线译码方式,并介绍利用Altera的Flex10k10E芯片实现该高速译码器硬件架构。测试和仿真结果表明,该高速译码器具有较高的译码速度和良好的译码性能。 相似文献
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Viterbi算法是卷积码的最优译码算法.设计并实现了一种高速(3,1,7)Viterbi译码器,该译码器由分支度量单元(BMU)、加比选单元(ACSU)、幸存路径存储单元(SMU)、控制单元(CU)组成.在StratixⅡ FPGA上实现、验证了该Viterbi译码器.验证结果表明,该译码器数据吞吐率达到231Mbit/s,在加性高斯白噪声(AWGN)信道下的误码率十分接近理论仿真值.与同类型Viterbi译码器比较,该译码器具有高速、硬件实现代价低的特点. 相似文献
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相对于符号取自GF(256)的RS码,现有文献对GF(4096)上RS码的性能和实现鲜有研究。将GF(4096)上若干不同码率的RS码进行了性能仿真对比。仿真结果表明,GF(4096)上的RS码具有很强的纠正随机和突发错误的能力。在误码率为10-6时,所仿真的3种不同码型的码字相对于BPSK调制分别取得了3.2 dB,3.7 dB和4 dB的编码增益。鉴于GF(4096)上RS码优良的性能,设计并实现了RS(4095,3935)码高速译码器。经过测试验证,该译码器具有设计的纠错能力,能稳定工作在150 MHz,其吞吐量达到1.8 Gb/s。 相似文献
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针对CCSDS标准中近地通信的LDPC码,为了提高准循环低密度奇偶校验(QC-LDPC)译码器的吞吐率和资源利用率,设计实现了一种低复杂度高速并行译码器。译码器整体采用流水线结构,通过改进校验节点与变量节点的更新方式,在不增加运算复杂度的情况下使信息处理所消耗的时间更短,压缩单次迭代所需时间,提高了译码器的吞吐量。以现场可编程门阵列(FPGA)作为实现平台,仿真并实现了基于归一化最小和算法的(8176,7154) LDPC译码器。结果表明,当译码器工作频率为200 MHz、迭代次数为10次的情况下,译码吞吐量可达到160 Mbit/s,满足大多数场景的应用需求。 相似文献
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介绍了数字电视广播中广泛采用的RS(204,188)译码器原理和FPGA实现方案,采用并行的三级流水线结构以提高速度,并根据Berlekamp-Massey(BM)算法对译码器进行了优化设计,减少了硬件消耗.译码器的最大时钟频率可以达到75MHz.译码器的性能仿真和FPGA实现验证了该方案的可行性. 相似文献
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本论文用可编程逻辑器件(FPGA)实现了一种低密度奇偶校验码(LDPC)的编译码算法.采用基于Q矩阵LDPC码构造方法,设计了具有线性复杂度的编码器. 基于软判决译码规则,采用全并行译码结构实现了码率为1/2、码长为40比特的准规则LDPC码译码器,并且通过了仿真测试.该译码器复杂度与码长成线性关系,与Turbo码相比更易于硬件实现,并能达到更高的传输速率. 相似文献
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通过有效地结合Constant-Log-MAP算法和En-Max-Log-MAP算法实现资源复用,文章研究了SNR自适应卷积Turbo码译码器的硬件设计,给出了关键模块的逻辑结构,并进行了硬件实现。逻辑综合和时序仿真验证表明,该设计在译码器的性能优化与节省片上资源方面有着优异的表现。 相似文献
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Wang Z. Cui Z. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(4):483-488
This paper presents a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check (QC-LDPC) codes using (modified) min-sum algorithm for decoding. In general, over 30% of memory can be saved over conventional partially parallel decoder architectures. Efficient techniques have been developed to reduce the computation delay of the node processing units and to minimize hardware overhead for parallel processing. The proposed decoder architecture can linearly increase the decoding throughput with a small percentage of extra hardware. Consequently, it facilitates the applications of LDPC codes in area/power sensitive high-speed communication systems 相似文献
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800Mbps准循环LDPC码译码器的FPGA实现 总被引:1,自引:0,他引:1
本文提出了一种适用于准循环低密度校验码的低复杂度的高并行度译码器架构。通常准循环低密度校验码不适于设计有效的高并行度高吞吐量译码器。我们通过利用准循环低密度校验码的奇偶校验矩阵的结构特点,将其转化为块准循环结构,从而能够并行化处理译码算法的行与列操作。使用这个架构,我们在Xilinx Virtex-5 LX330 FPGA上实现了(8176,7154)有限几何LDPC码的译码器,在15次迭代的条件下其译码吞吐量达到800Mbps。 相似文献
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循环移位置换单元是准循环LDPC码的部分并行译码器的重要组成部分。该文研究并证明了Reverse Banyan交换结构在实现信息循环移位时各个基本交换单元的连接规律。基于该规律设计了基于可预置选路算法的无阻塞循环移位置换结构。相比Benes交换结构和Reverse Banyan交换结构,提高了信息循环移位交换的速率,且占用较少的硬件资源和面积。最后设计了一个出线转换单元,该单元适用于各种循环移位交换结构。 相似文献
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Random linear network coding is an efficient technique for disseminating information in networks, but it is highly susceptible to errors. Kötter-Kschischang (KK) codes and Mahdavifar-Vardy (MV) codes are two important families of subspace codes that provide error control in noncoherent random linear network coding. List decoding has been used to decode MV codes beyond half distance. Existing hardware implementations of the rank metric decoder for KK codes suffer from limited throughput, long latency and high area complexity. The interpolation-based list decoding algorithm for MV codes still has high computational complexity, and its feasibility for hardware implementations has not been investigated. In this paper we propose efficient decoder architectures for both KK and MV codes and present their hardware implementations. Two serial architectures are proposed for KK and MV codes, respectively. An unfolded decoder architecture, which offers high throughput, is also proposed for KK codes. The synthesis results show that the proposed architectures for KK codes are much more efficient than rank metric decoder architectures, and demonstrate that the proposed decoder architecture for MV codes is affordable. 相似文献
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In this paper, we propose hardware architecture for a high‐speed context‐adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode 1920×1088 30 fps video in real time at a 30.8 MHz clock. 相似文献
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《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(4):582-587
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Yongmei Dai Zhiyuan Yan Ning Chen 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2008,16(5):565-578
Efficient hardware implementation of low-density parity-check (LDPC) codes is of great interest since LDPC codes are being considered for a wide range of applications. Recently, overlapped message passing (OMP) decoding has been proposed to improve the throughput and hardware utilization efficiency (HUE) of decoder architectures for LDPC codes. In this paper, we first study the scheduling for the OMP decoding of LDPC codes, and show that maximizing the throughput gain amounts to minimizing the intra- and inter-iteration waiting times. We then focus on the OMP decoding of quasi-cyclic (QC) LDPC codes. We propose a partly parallel OMP decoder architecture and implement it using FPGA. For any QC LDPC code, our OMP decoder achieves the maximum throughput gain and HUE due to overlapping, hence has higher throughput and HUE than previously proposed OMP decoders while maintaining the same hardware requirements. We also show that the maximum throughput gain and HUE achieved by our OMP decoder are ultimately determined by the given code. Thus, we propose a coset-based construction method, which results in QC LDPC codes that allow our optimal OMP decoder to achieve higher throughput and HUE. 相似文献
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卷积码是一种重要的前向纠错信道编码方式,其纠错性能常常优于分组码,且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块,译码器采用全并行结构,译码速度快。阐述了编译码器各模块的设计原理,并在ModelSim给出各模块的仿真测试结果。同时对译码器进行纠错性能测试,测试结果表明该Viterbi译码器有良好的纠错性能。 相似文献