共查询到19条相似文献,搜索用时 78 毫秒
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基于ARM平台设计了一种针对磁电式转速传感系统的高稳定度实时转速测量方法,该方法能够有效消除传统转速测量方法无法克服的由计数误差和脉冲发生器的加工误差引起的转速测量波动。针对所设计的转速测量方法进行试验,结果表明,所设计的转速测量方法能有效消除测量结果波动,且实现简单,动态跟踪效果好。 相似文献
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论文从现代软件系统设计的趋势出发,引出架构设计及其目标:设计出“高内聚,低耦合” 的应用系统。就应用成熟开源框架Struts,Spring 和Hibernate 进行架构设计如何做到高内聚、低耦合展开分析,得出结论。 相似文献
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杯形波动陀螺具有极高的Q值,一般都在20 000以上,因此仅仅0.3‰的驱动信号频率误差都会使陀螺机械灵敏度降低99%以上。针对这一问题实现了一种基于直接数字频率合成的高性能正弦信号生成算法,以此为基础从统计域的角度对引起频率源抖动的根源进行了估计分析,并给出了一种具有针对性的抖动分离方法,为频率源的设计提供了理论指导和依据,降低了修正和优化频率源的盲目性。由阿伦方差可知采用抖动分离方法优化后,频率源短期稳定度提高约为20%。通过对设计的频率源进行一系列时域和频域测试分析,证明最终的驱动信号频率稳定在1 mHz以内。 相似文献
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基于翻转电压跟随器(Flipped Voltage Follower,FVF)的拓扑结构,实现了一种低功耗高线性的跨导器,跨导值可由控制电压精确改变。运用此跨导单元设计了一种适用于无线收发机系统的多频带Gm-C低通滤波器。该滤波器是由双二次节级联构成的六阶巴特沃斯型滤波器,可实现70 kHz,140 kHz和210 kHz多频带选择。采用SMIC 0.18 μm CMOS工艺设计的滤波器的线性度IIP3大于22.6 dBm,在1.8 V电源电压下消耗的功耗为1.37 mW。 相似文献
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This paper presents a novel,semi-transparent structure to implement single-edge and dual-edge triggered flip-flops.These two novel flip-flops can achieve high speed and low power due to their short data paths and fewer redundant transitions.Simulation results show that the proposed semi-transparent flip-flop and dual-edge triggered semi-transparent flip-flop perform best compared with conventional flip-flops.STFF reduces the power-delay-product 33.1% compared with Antonio’s sense amplifier based flip-flop.DSTFF improves the PDP 9.1% and 47.8% as compared with dual-edge triggered sense amplifier based flip-flop and high speed dual-edge triggered modified hybrid latch flip-flop respectively. 相似文献
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This paper presents a novel,semi-transparent structure to implement single-edge and dual-edge triggered flip-flops.These two novel flip-flops can achieve high speed and low power due to their short data paths and fewer redundant transitions.Simulation results show that the proposed semi-transparent flip-flop and dual-edge triggered semi-transparent flip-flop perform best compared with conventional flip-flops.STFF reduces the power-delay-product 33.1% compared with Antonio’s sense amplifier based flip-flop.DSTFF improves the PDP 9.1% and 47.8% as compared with dual-edge triggered sense amplifier based flip-flop and high speed dual-edge triggered modified hybrid latch flip-flop respectively. 相似文献
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一种高线性调整率无电容型LDO的设计 总被引:1,自引:0,他引:1
提出了一种1.8 V、70 mA片上集成的低功耗无电容型LDO(Low Dropout)电路。电路中采用了一级增益自举运放作为误差放大器,通过消除零点的密勒补偿技术提高了环路稳定性;带隙基准源(BGR)采用了线性化VBE技术进行高阶补偿,可以获得温度稳定性更好的BGR,降低了BGR对线性调整率的影响。该设计采用HHNEC 0.13μm CMOS工艺(其中VTHN≈0.78 V、VTHP≈-0.9 V),整个芯片面积为0.33 mm×0.34 mm。测试结果显示:在2.5 V-5.5 V电源供电下,LDO输出的线性调整率小于2.14 mV/V,负载调整率小于1.56 mV/mA;在正常工作模式下,整个LDO消耗56μA静态电流(其中测试用的放大器消耗电流约18μA)。 相似文献
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The flash memory technology meets physical and technical obstacles in further scaling. New structures and new materials are implemented as possible solutions. This paper focuses on two kinds of new flash cells for high density and low power memory applications based on the vertical channel double gate structure. The proposed VD-NROM with dual-nitride-trapping-layer and vertical structure can achieve four-bit-per-cell storage capability. And the proposed VSAS-FG cell benefits the high programming efficiency, low power and high density capability, which can be realized without any additional mask and can achieve the self-alignment of the split-gate channel and the floating-gate. The two novel flash cell structures can be considered as potential candidates for different flash memory applications. 相似文献
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为了满足基于高性能双核MPC8641D处理器的高功耗嵌入式单板计算机的电源设计,分析了处理器的供电要求和单板计算机的整体电路功能,开展了基于多种电源转换芯片的供电设计,解决了高功耗嵌入式单板计算机的供电问题.通过设计基于可编程逻辑器件CPLD的上电时序控制器,实现了多种电源之间的加电时序控制以及复位管理.单板计算机的实际应用结果表明该电源设计稳定可靠、灵活通用. 相似文献