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本文提出了一种基于65nm CMOS标准工艺、采用粗调和细调相结合的低噪声环形压控振荡器。论文分析了环形振荡器中的直接频率调制机理,并采用开关电容阵列来减小环形压控振荡器的增益从而抑制直接频率调制效应。开关电容采用电容密度较高的二维叠层MOM电容使该压控振荡器与标准的CMOS工艺兼容。所设计压控振荡器的频率范围为480MHz~1100MHz,调谐范围为78%,测试得到输出频率为495MHz时的相位噪声为-120dBc/Hz@1MHz。该压控振荡器在1.2V的偏压下的功耗为3.84mW,相应的优值(FOM)为-169dBc/Hz。 相似文献
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采用标准的0.13μm CMOS工艺实现了0.5V电源电压,3GHz LC压控振荡器。为了适应低电压工作,并实现低相位噪声,该压控振荡器采用了NMOS差分对的电压偏置振荡器结构,去除尾电流,以尾电感代替,采用感性压控端,增加升压电路结构使变容管的一端升压,这样控制电压变化范围得到扩展。测试结果显示,当电源电压为0.5V,振荡频率为3.126GHz时,在相位噪声为-113.83dBc/Hz@1MHz,调谐范围为12%,核心电路功耗仅1.765mW,该振荡器的归一化品质因数可达-186.2dB,芯片面积为0.96mm×0.9mm。 相似文献
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Zhi-Qiang Lu Jian-Guo Ma Feng-Chang Lai 《Analog Integrated Circuits and Signal Processing》2006,49(1):27-30
A 900-MHz two-stage CMOS voltage controlled ring oscillator (VCRO) with quadrature output is presented. The circuit is designed
in a 0.18-um CMOS technology and operated on a 1.8-V supply voltage. The VCRO have a tuning range of 730 MHz to 1.43 GHz and
good tuning linearity. Between 0 V and 1.1 V of control voltage, the gain of VCRO is around −620 MHz/V. At 900 MHz, the phase
noise of the VCRO is −106.1 dBc/Hz at 600-KHz frequency offset with power consumption of 65.5 mW. 相似文献
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A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning 总被引:1,自引:0,他引:1
《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(4):571-577
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A circuit of a ring voltage controlled oscillator (VCO), which is to be used in high-speed phase-locked loop (PLL) systems integrated into programmable logic integrated circuits, is proposed. The maximum operating frequency of a VCO in 180 nm CMOS is shown by simulation to be able to reach 2 GHz in all operating conditions with the phase noise being ?99 dB/Hz and detuning frequency being 1 MHz. 相似文献
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A low jitter All-Digital Phase-Locked Loop (ADPLL) used as a clock generator is designed. The Digital-Controlled Oscillator (DCO) for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function (ISF) analysis, an effective way is proposed to reduce the ADPLL's jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO's output frequency is 188MHz. 相似文献
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A 1-V 5.2-GHz CMOS synthesizer for WLAN applications 总被引:1,自引:0,他引:1
A 1-V CMOS frequency synthesizer designed for WLAN 802.11a is presented. Novel circuit designs are demonstrated in the system for low-voltage applications including design of voltage-controlled oscillator and design of programmable divider. Implemented in a 0.18-/spl mu/m CMOS process and operated at 1-V supply voltage, the synthesizer measures phase noise of -136 dBc/Hz at a frequency offset of 20 MHz and spur performance of less than -80 dBc at an offset of 11 MHz. The synthesizer dissipates 27.5 mW from a single 1-V supply and occupies a chip area of 1.03 mm/sup 2/. 相似文献
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A rotary traveling-wave oscillator (RTWO) targeted at 5.8 GHz band operation is designed and fabricated using standard 0.18 μm CMOS technology. Both simulation and measurement results are presented. The chip size including pads is 1.5 × 1.5 mm2. The measured output power at a frequency of 5.285 GHz is 6.68 dBm, with a phase noise of-102 dBc/Hz at 1 MHz offset from the carrier. 相似文献
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A simple light-sensitive CMOS ring oscillator, the oscillation frequency of which depends on the chip ambient illumination, is presented. An experimental 21-stage ring oscillator fabricated in 0.5 μm CMOS changes the pulse frequency from 50 Hz in total darkness to 2 MHz in extreme bright ambient at Vdd=1 V 相似文献
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《Microwave and Wireless Components Letters, IEEE》2008,18(8):563-565
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A differential complementary LC voltage controlled oscillator(VCO) with high Q on-chip inductor is presented.The parallel resonator of the VCO consists of inversion-mode MOS(I-MOS) capacitors and an on-chip inductor.The resonator Q factor is mainly limited by the on-chip inductor.It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz.The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process,and the chip area is 1.0×0.8 mm~2.The free-running frequency is from 5.73 to 6.35 GHz.When oscillating at 6.35 GHz,the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz.The figure of merit of the proposed VCO is -192.13 dBc/Hz. 相似文献
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A 10 GHz ring voltage controlled oscillator (VCO) has been designed and implemented in 0.12 /spl mu/m CMOS technology. A source capacitively coupled current amplifier (SC3A) is adopted to realise this VCO. It can operate from 8.4 GHz up to 10.6 GHz with a phase noise of about -85 dBc/Hz at 1 MHz frequency offset. With the 1.5 V supply voltage, the current consumption is about 35 mA. 相似文献
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A phase-locked loop(PLL) frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator(VCO) is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm~2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz. 相似文献
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研究了一种基于以太网物理层时钟同步的高带宽低噪声压控振荡器(VCO),该VCO采用交叉耦合的电流饥饿型环形振荡器,通过级联11级环路电路和改善其控制电压变换电路,优化了VCO的输出频率范围以及降低了输出时钟的相位噪声,完全满足以太网物理层芯片时钟电路的性能指标。基于TSMC3.3V0.25μmCMOS工艺的仿真结果表明,中心频率为250MHz时,压控增益为300MHz/V,其线性区覆盖范围是60~480MHz,在偏离中心频率600kHz处的相位噪声为-108dBc。 相似文献
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A new differential delay cell with a complementary current control to increase the control voltage range as well as the operation frequency is proposed for low-voltage operation. The new differential delay cell is employed in a four-stage voltage-controlled ring oscillator (VCRO). The VCRO is implemented using 0.18 m 1P6M CMOS process and 1.8 V supply voltage. Measured results show that a wide operation frequency range from 5.36 to 3.03 GHz is achieved for the full range control voltage from 0 to 1.8 V. Measured phase noise is 107 dBc/Hz at 1 MHz offset from the 5.22 GHz centre frequency. 相似文献
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A low jitter,low spur multiphase phase-locked loop(PLL) for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator(VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the l... 相似文献