共查询到20条相似文献,搜索用时 31 毫秒
1.
A simplified analytical expression for the temperature dependent saturated I D-V D characteristics of hydrogenated amorphous silicon (a-Si:H) thin-film transistors, between -50°C and 90°C, is presented and experimentally verified. The results show that the experimental transfer and output characteristics at several temperatures are easily modeled by a single equation. The model is based on three functions obtained from the experimental data of I D versus V G, over a range of temperature. Theoretical results confirm the simple form of the model in terms of the device geometry. As the temperature increased, the saturated drain current increased and, at a fixed gate voltage the device saturated at increasingly larger drain voltages while the threshold voltage decreased. Good agreement between the measured data and the model was obtained up to 363 K. Also observed at temperatures larger than 363 K was a decrease in I D and more severe gate voltage hysteresis characteristics 相似文献
2.
Malik R.J. Chand N. Nagle J. Ryan R.W. Alavi K. Cho A.Y. 《Electron Device Letters, IEEE》1992,13(11):557-559
Temperature-dependent measurements from 25 to 125°C have been made of the DC I -V characteristics of HBTs with GaAs and In0.53Ga0.47As collector regions. It was found that the GaAs HBTs have very low output conductance and high collector breakdown voltage BV CEO>10 V at 25°C, which increases with temperature. In striking contrast, the In0.53Ga0.47As HBTs have very high output conductance and low BV CEO~2.5 V at 25°C, which actually decreases with temperature. This different behavior is explained by the >104 higher collector leakage current, I CO, in In0.53Ga0.47As compared to GaAs due to bandgap differences. It is also shown that device self-heating plays a role in the I -V characteristics 相似文献
3.
Peransin J.-M. Vignaud P. Rigaud D. Vandamme L.K.J. 《Electron Devices, IEEE Transactions on》1990,37(10):2250-2253
The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S I/I 2 versus the effective gate voltage V G=V GS-V off shows three regions which are explained. The observed dependencies are S I/I 2∝V G m with the exponents m =-1, -3, 0 with increasing values of V G. The model explains m =-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m =0 at large V G or V GS≅0 is due to the dominant contribution of the series resistance. In the region at intermediate V G , m =-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance 相似文献
4.
The authors show that the Taylor-series coefficients of a FET's gate/drain I /V characteristic, which is used to model this nonlinearity for Volterra-series analysis, can be derived from low-frequency RF measurements of harmonic output levels. The method circumvents many of the problems encountered in using DC measurements to characterize this nonlinearity. This method was used to determine the incremental gate I /V characteristic of a packaged Aventek AT10650-5 MESFET biased at a drain voltage of 3 V and drain current of 20 mA. The FET's transconductance was measured at DC, and its small-signal equivalent circuit (including the package parasitics) was determined by adjusting its circuit element values until good agreement between calculated and measured S parameters was obtained. The FET was then installed in a low-frequency test fixture. Excellent results were obtained 相似文献
5.
A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I g-V g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I g- V g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I g-V g measurements 相似文献
6.
The authors report on the off-state gate current (I g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I g at drain voltages as low as 4 V and an I g injection efficiency reaching 0.8, as compared to 8.5 V and 10-7 in SiO2 devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure 相似文献
7.
Slotboom J.W. Streutker G. Pruijmboom A. Gravesteijn D.J. 《Electron Device Letters, IEEE》1991,12(9):486-488
Parasitic energy barriers can easily be introduced during processing. Measurements and calculations of experimental n-p-n HBTs (heterojunction bipolar transistors) are presented, showing that a parasitic conduction-band barrier at the base-collector junction reduces the collector current and the cutoff frequency. A simple analytical model explains the f T degradation, caused by the reduction of the collector current and a pileup of minority carriers in the base. With the model the effective height and width of the barrier can also be derived from the measured collector current enhancement factor I C(SiGe)/I C(Si) 相似文献
8.
Busta H.H. Pogemiller J.E. Zimmerman B.J. 《Electron Devices, IEEE Transactions on》1993,40(8):1537-1542
The field at the tip of a field emitter triode can be expressed by E =βV g+γV c, where V g and V c the gate and collector voltages, respectively. For small gate diameters and tips below or in the plane of the gate and/or large tip-to-collector distances, γV c<<βV g. The-device is operated in the gate-induced field emission mode and the corresponding I -V c curves are pentode-like. By increasing the gate diameter and/or recessing the gates from the tips, collector-assisted operation can be achieved at reasonable collector voltages. Results are presented for two devices with gate diameters of 3.6 and 2.0 μm. By obtaining γ at different emitter-to-collector distances, I -V c and transconductance g m-V g curves are calculated and compared with experimental results. It is shown that as a consequence of collector-assisted operation, the transconductance of a device can be increased significantly 相似文献
9.
Dependence of ionization current on gate bias in GaAs MESFETs 总被引:1,自引:0,他引:1
Canali C. Neviani A. Tedesco C. Zanoni E. Centronio A. Lanzieri C. 《Electron Devices, IEEE Transactions on》1993,40(3):498-501
The nonmonotonic behavior of gate current I g as a function of gate-to-source voltage V gs is reported for depletion-mode double-implant GaAs MESFETs. Experiments and numerical simulations show that the main contribution to I g (in the range of drain biases studied) comes from impact-ionization-generated holes collected at the gate electrode, and that the bell shape of the I g(V gs) curve is strongly related to the drop of the electric field in the channel of the device as V gs is moved towards positive values 相似文献
10.
Monte Carlo methods are used to compare electronic transport and device behavior in n+-AlxGa1-xAs/GaAs modulation-doped field-effect transistors (MODFETs) at 300 K for x =0.10, 0.15, 0.22, 0.30, 0.35, and 0.40. The differences between the x =0.22 and x =0.30 MODFETs with respect to parasitic conduction in AlxGa1-xAs, gate currents, and switching times, are of particular interest. The donor-related deep levels in AlxGa1-xAs, are disregarded by assuming all donors to be fully ionized, and the focus is only on the confinement and transport of the carriers. The following quantities are studied in detail: transfer characteristics (I D versus V G), transconductance (g m), switching speeds (τON), parasitic conduction in AlxGa 1-xAs, gate current (I G), average electron velocities and energies in GaAs and AlxGa1-x As, electron concentration in the device domain, k -space transfer (to low mobility L and X valleys), and details of the real-space transfer process 相似文献
11.
Zanoni E. Malik R. Pavan P. Nagle J. Paccagnella A. Canali C. 《Electron Device Letters, IEEE》1992,13(5):253-255
Impact ionization phenomena in the collector region of AlGaAs/GaAs heterojunction bipolar transistors give rise to base current reduction and reversal. These phenomena can be characterized by extracting the M -1 coefficient, which can be evaluated by measuring base current changes. Measurements of M -1 are affected at low current densities by the presence of the collector-base junction reverse current I CBO. At high current densities, three effects contribute to lower the measured M -1 value: voltage drops due to collector (R C) and base (R B) parasitic resistances, device self-heating, and lowering of the base-collector junction electric field due to mobile carriers. By appropriately choosing the emitter current value, parasitic phenomena are avoided and the behavior of M -1 as a function of the collector-base voltage V CB in AlGaAs/GaAs HBTs is accurately characterized 相似文献
12.
The fabrication and characterization of a 0.25-μm-gate, ion-implanted GaAs MESFET with a maximum current-gain cutoff frequency f t of 126 GHz is reported. Extrapolation of current gains from bias-dependent S -parameters at 70-100% of I dss yields f 1's of 108-126 GHz. It is projected that an f 1 of 320 GHz is achievable with 0.1-μm-gate GaAs MESFETs. This demonstration of f 1's over 100 GHz with practical 0.25-μm gate length substantially advances the high-frequency operation limits of short-gate GaAs MESFETs 相似文献
13.
Gate current in OFF-state MOSFET 总被引:1,自引:0,他引:1
The source of the gate current in MOSFETs due to an applied drain voltage with the gate grounded is studied. It is found that for 100-Å or thinner oxide, the gate current is due to Fowler-Nordheim (F-N) tunneling electrons from the gate. With increasing oxide thickness, hot-hole injection becomes the dominant contribution to the gate current. This gate current can cause I D walkout, which is a decrease in the gate-induced drain leakage current, and hole trapping, which becomes important for device degradation study. It can also be used to advantage in EPROM (erasable programmable read-only memory) erasure 相似文献
14.
The light-to-current (L -I ) and light-to-voltage (L -V ) differential nonlinearities in the simple network of a customary LED and an external resistor R in series are analyzed and calculated theoretically and compared with experimental data. Particular emphasis is placed on the influence of the log-arithmetic slope ν of the L -I characteristic and the bias current I upon the ratio of the corresponding nonlinearity parameters. It is thus deduced that, for a given optical power P , over superlinear portions of the L -I curve (ν>1) the L -I linearity is typically better than its corresponding L -V linearity. On the contrary, when the L -I dependence is sublinear (ν<1) the voltage driving scheme may ensure for the R -LED network, or the LED alone, a local L -V response much more linear than the L -I response, provided that appropriate (optimum) I and/or R values are chosen 相似文献
15.
Self-aligned high-frequency InP/InGaAs double heterojunction bipolar transistors (DHBTs) have been fabricated on a Si substrate. A current gain of 40 was obtained for a DHBT with an emitter dimension of 1.6 μm×19 μm. The S parameters were measured for various bias points. In the case of I C=15 mA, f T was 59 GHz at V CE=1.8 V, and f max was 69 GHz at V CE=2.3 V. Due to the InP collector, breakdown voltage was so high that a V CE of 3.8 V was applied for I C=7.5 mA in the S -parameter measurements to give an f T of 39 GHz and an f max of 52 GHz 相似文献
16.
An I -V model for short gate-length MESFETs operated in the turn-on region is proposed, in which the two-dimensional potential distributions contributed by the depletion-layer charges under the gate and in the ungated region are separately obtained by conventional 1-D approximation and the Green's function solution technique. Moreover, the bias-dependent parasitic resistances due to the modulation of the depletion layer in the ungated region for non-self-alignment MESFETs are also taken into account in the developed I -V model. It is shown that good agreement is obtained between the I -V model and the results of 2-D numerical analysis. Moreover, comparisons between the proposed analytical model and the experimental data are made, and excellent agreement is obtained 相似文献
17.
Poly-Si resistors with an unimplanted channel region (and with n-type source/drain regions) can exhibit a nonhyperbolic sine (non-sinh) I -V characteristic at low V DS and an activation energy which is not simply decreasing monotonically with increasing V DS. These phenomena are not explained by conventional poly-Si resistor models. To describe these characteristics, a self-consistent model which includes the effects of a reverse-biased diode at the drain end is presented. Numerical simulation results show excellent agreement with experiment in regard to the shape of the I -V characteristic and of the effective activation energy as a function of V DS 相似文献
18.
Lee W.-S. Enoki T. Yamahata S. Matsuoka Y. Ishibashi T. 《Electron Devices, IEEE Transactions on》1992,39(12):2694-2700
A self-aligned process is developed to obtain submicrometer high-performance AlGaAs/GaAs heterojunction bipolar transistors (HBTs) which can maintain a high current gain for emitter sizes on the order of 1 μm2. The major features of the process are incorporation of an AlGaAs surface passivation structure around the entire emitter-base junction periphery to reduce surface recombination and reliable removal of base metal (Ti/W) deposits from the sidewall by electron cyclotron resonance (ECR) plasma deposition of oxide and ECR plasma etching by NF3. A DC current gain of more than 30 can be obtained for HBTs with an emitter-base junction area of 0.5×2 μm2 at submilliampere collector currents. The maximum f T and f max obtained from a 0.5×2 μm2 emitter HBT are 46 and 42 GHz, respectively at I C=1.5 and more than 20 GHz even at I C=0.1 mA 相似文献
19.
《Electron Devices, IEEE Transactions on》1990,37(1):153-158
The fabrication of a silicon heterojunction microwave bipolar transistor with an n+ a-Si:H emitter is discussed, and experimental results are given. The device provides a base sheet resistance of 2 kΩ/□ a base width 0.1 μm, a maximum current gain of 21 (V CE=6 V, I c=15 mA), and an emitter Gummel number G E of about 1.4×1014 Scm-4. From the measured S parameters, a cutoff frequency f t of 5.5 GHz and maximum oscillating frequency f max of 7.5 GHz at V CE=10 V, I c=10 mA are obtained 相似文献
20.
A unified and process-independent MOSFET model for accurate prediction of the I -V characteristics and the threshold voltages of narrow-gate MOSFETs is discussed. It is based on several enhancements of the SPICE2 LEVEL3 MOS model and the author's previous subthreshold I -V model. The expressions achieved for the drain current hold in the subthreshold, transition, and strong inversion regions. A continuous model is proposed for the transition region, using a scheme that ensures that both the current and conductance are continuous and will not cause convergence problems for circuit simulation applications. All of the modeled parameters are taken from experimentally measured I -V characteristics and preserve physical meaning. Comparisons between the measured and modeled I -V characteristics show excellent agreement for a wide range of channel widths and biases. The model is well suited for circuit simulation in SPICE 相似文献