A model for the temperature-dependent saturated ID-VD characteristics of an a-Si:H thin-filmtransistor

A simplified analytical expression for the temperature dependent saturated I_D-V_D characteristics of hydrogenated amorphous silicon (a-Si:H) thin-film transistors, between -50°C and 90°C, is presented and experimentally verified. The results show that the experimental transfer and output characteristics at several temperatures are easily modeled by a single equation. The model is based on three functions obtained from the experimental data of I_D versus V_G, over a range of temperature. Theoretical results confirm the simple form of the model in terms of the device geometry. As the temperature increased, the saturated drain current increased and, at a fixed gate voltage the device saturated at increasingly larger drain voltages while the threshold voltage decreased. Good agreement between the measured data and the model was obtained up to 363 K. Also observed at temperatures larger than 363 K was a decrease in I_D and more severe gate voltage hysteresis characteristics     

Temperature dependence of common-emitter I-V andcollector breakdown voltage characteristics in AlGaAs/GaAs andAlInAs/GaInAs HBT's grown by MBE

Temperature-dependent measurements from 25 to 125°C have been made of the DC I-V characteristics of HBTs with GaAs and In_0.53Ga_0.47As collector regions. It was found that the GaAs HBTs have very low output conductance and high collector breakdown voltage BV_CEO>10 V at 25°C, which increases with temperature. In striking contrast, the In_0.53Ga_0.47As HBTs have very high output conductance and low BV_CEO~2.5 V at 25°C, which actually decreases with temperature. This different behavior is explained by the >10⁴ higher collector leakage current, I_CO, in In_0.53Ga_0.47As compared to GaAs due to bandgap differences. It is also shown that device self-heating plays a role in the I-V characteristics     

1/f noise in MODFETs at low drain bias

The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S_I/I² versus the effective gate voltage V_G=V_GS-V_off shows three regions which are explained. The observed dependencies are S_I/I²∝V_G ^m with the exponents m=-1, -3, 0 with increasing values of V_G. The model explains m =-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m=0 at large V_G or V_GS≅0 is due to the dominant contribution of the series resistance. In the region at intermediate V_G , m=-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance     

Modeling the gate I/V characteristic of a GaAsMESFET for Volterra-series analysis

The authors show that the Taylor-series coefficients of a FET's gate/drain I/V characteristic, which is used to model this nonlinearity for Volterra-series analysis, can be derived from low-frequency RF measurements of harmonic output levels. The method circumvents many of the problems encountered in using DC measurements to characterize this nonlinearity. This method was used to determine the incremental gate I/V characteristic of a packaged Aventek AT10650-5 MESFET biased at a drain voltage of 3 V and drain current of 20 mA. The FET's transconductance was measured at DC, and its small-signal equivalent circuit (including the package parasitics) was determined by adjusting its circuit element values until good agreement between calculated and measured S parameters was obtained. The FET was then installed in a low-frequency test fixture. Excellent results were obtained     

Characterization of oxide trap and interface trap creation duringhot-carrier stressing of n-MOS transistors using the floating-gatetechnique

A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I_g-V_g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I_g- V_g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I_g-V _g measurements     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

Parasitic energy barriers in SiGe HBTs

Parasitic energy barriers can easily be introduced during processing. Measurements and calculations of experimental n-p-n HBTs (heterojunction bipolar transistors) are presented, showing that a parasitic conduction-band barrier at the base-collector junction reduces the collector current and the cutoff frequency. A simple analytical model explains the f_T degradation, caused by the reduction of the collector current and a pileup of minority carriers in the base. With the model the effective height and width of the barrier can also be derived from the measured collector current enhancement factor I_C(SiGe)/I_C(Si)     

Dependence of ionization current on gate bias in GaAs MESFETs

The nonmonotonic behavior of gate current I_g as a function of gate-to-source voltage V_gs is reported for depletion-mode double-implant GaAs MESFETs. Experiments and numerical simulations show that the main contribution to I_g (in the range of drain biases studied) comes from impact-ionization-generated holes collected at the gate electrode, and that the bell shape of the I_g(V_gs) curve is strongly related to the drop of the electric field in the channel of the device as V_gs is moved towards positive values     

Collector-assisted operation of micromachined field-emitter triodes

The field at the tip of a field emitter triode can be expressed by E=βV_g+_γV _c, where V_g and V_c the gate and collector voltages, respectively. For small gate diameters and tips below or in the plane of the gate and/or large tip-to-collector distances, _γV_c<<βV _g. The-device is operated in the gate-induced field emission mode and the corresponding I-V_c curves are pentode-like. By increasing the gate diameter and/or recessing the gates from the tips, collector-assisted operation can be achieved at reasonable collector voltages. Results are presented for two devices with gate diameters of 3.6 and 2.0 μm. By obtaining γ at different emitter-to-collector distances, I-V_c and transconductance g_m-V_g curves are calculated and compared with experimental results. It is shown that as a consequence of collector-assisted operation, the transconductance of a device can be increased significantly     

Monte Carlo study of GaAs/Alx Ga1-xAsMODFETs: effects of AlxGa1-xAs composition

Monte Carlo methods are used to compare electronic transport and device behavior in n⁺-Al_xGa_1-xAs/GaAs modulation-doped field-effect transistors (MODFETs) at 300 K for x =0.10, 0.15, 0.22, 0.30, 0.35, and 0.40. The differences between the x=0.22 and x=0.30 MODFETs with respect to parasitic conduction in Al_xGa_1-xAs, gate currents, and switching times, are of particular interest. The donor-related deep levels in Al_xGa_1-xAs, are disregarded by assuming all donors to be fully ionized, and the focus is only on the confinement and transport of the carriers. The following quantities are studied in detail: transfer characteristics (I_D versus V _G), transconductance (g_m), switching speeds (τ_ON), parasitic conduction in Al_xGa _1-xAs, gate current (I_G), average electron velocities and energies in GaAs and Al_xGa_1-x As, electron concentration in the device domain, k-space transfer (to low mobility L and X valleys), and details of the real-space transfer process     

Negative base current and impact ionization phenomena inAlGaAs/GaAs HBTs

Impact ionization phenomena in the collector region of AlGaAs/GaAs heterojunction bipolar transistors give rise to base current reduction and reversal. These phenomena can be characterized by extracting the M-1 coefficient, which can be evaluated by measuring base current changes. Measurements of M-1 are affected at low current densities by the presence of the collector-base junction reverse current I_CBO. At high current densities, three effects contribute to lower the measured M-1 value: voltage drops due to collector (R_C) and base (R_B) parasitic resistances, device self-heating, and lowering of the base-collector junction electric field due to mobile carriers. By appropriately choosing the emitter current value, parasitic phenomena are avoided and the behavior of M-1 as a function of the collector-base voltage V_CB in AlGaAs/GaAs HBTs is accurately characterized     

Quarter-micrometer gate ion-implanted GaAs MESFET's with an f1 of 126 GHz

The fabrication and characterization of a 0.25-μm-gate, ion-implanted GaAs MESFET with a maximum current-gain cutoff frequency f_t of 126 GHz is reported. Extrapolation of current gains from bias-dependent S-parameters at 70-100% of I _dss yields f₁'s of 108-126 GHz. It is projected that an f₁ of 320 GHz is achievable with 0.1-μm-gate GaAs MESFETs. This demonstration of f₁'s over 100 GHz with practical 0.25-μm gate length substantially advances the high-frequency operation limits of short-gate GaAs MESFETs     

Gate current in OFF-state MOSFET

The source of the gate current in MOSFETs due to an applied drain voltage with the gate grounded is studied. It is found that for 100-Å or thinner oxide, the gate current is due to Fowler-Nordheim (F-N) tunneling electrons from the gate. With increasing oxide thickness, hot-hole injection becomes the dominant contribution to the gate current. This gate current can cause I_D walkout, which is a decrease in the gate-induced drain leakage current, and hole trapping, which becomes important for device degradation study. It can also be used to advantage in EPROM (erasable programmable read-only memory) erasure     

Light-to-input nonlinearities in an R-LED series network

The light-to-current (L-I) and light-to-voltage (L-V) differential nonlinearities in the simple network of a customary LED and an external resistor R in series are analyzed and calculated theoretically and compared with experimental data. Particular emphasis is placed on the influence of the log-arithmetic slope ν of the L-I characteristic and the bias current I upon the ratio of the corresponding nonlinearity parameters. It is thus deduced that, for a given optical power P, over superlinear portions of the L-I curve (ν>1) the L-I linearity is typically better than its corresponding L-V linearity. On the contrary, when the L-I dependence is sublinear (ν<1) the voltage driving scheme may ensure for the R-LED network, or the LED alone, a local L-V response much more linear than the L-I response, provided that appropriate (optimum) I and/or R values are chosen     

High-frequency InP/InGaAs double heterojunction bipolar transistorson Si substrate

Self-aligned high-frequency InP/InGaAs double heterojunction bipolar transistors (DHBTs) have been fabricated on a Si substrate. A current gain of 40 was obtained for a DHBT with an emitter dimension of 1.6 μm×19 μm. The S parameters were measured for various bias points. In the case of I_C=15 mA, f _T was 59 GHz at V_CE=1.8 V, and f _max was 69 GHz at V_CE=2.3 V. Due to the InP collector, breakdown voltage was so high that a V_CE of 3.8 V was applied for I_C=7.5 mA in the S-parameter measurements to give an f_T of 39 GHz and an f_max of 52 GHz     

A new I-V model for short gate-length MESFET's

An I-V model for short gate-length MESFETs operated in the turn-on region is proposed, in which the two-dimensional potential distributions contributed by the depletion-layer charges under the gate and in the ungated region are separately obtained by conventional 1-D approximation and the Green's function solution technique. Moreover, the bias-dependent parasitic resistances due to the modulation of the depletion layer in the ungated region for non-self-alignment MESFETs are also taken into account in the developed I-V model. It is shown that good agreement is obtained between the I-V model and the results of 2-D numerical analysis. Moreover, comparisons between the proposed analytical model and the experimental data are made, and excellent agreement is obtained     

Modeling of nonhyperbolic sine I-Vcharacteristics in poly-Si resistors

Poly-Si resistors with an unimplanted channel region (and with n-type source/drain regions) can exhibit a nonhyperbolic sine (non-sinh) I-V characteristic at low V_DS and an activation energy which is not simply decreasing monotonically with increasing V_DS. These phenomena are not explained by conventional poly-Si resistor models. To describe these characteristics, a self-consistent model which includes the effects of a reverse-biased diode at the drain end is presented. Numerical simulation results show excellent agreement with experiment in regard to the shape of the I -V characteristic and of the effective activation energy as a function of V_DS     

A complete model of the I-V characteristics fornarrow-gate MOSFETs

A unified and process-independent MOSFET model for accurate prediction of the I-V characteristics and the threshold voltages of narrow-gate MOSFETs is discussed. It is based on several enhancements of the SPICE2 LEVEL3 MOS model and the author's previous subthreshold I-V model. The expressions achieved for the drain current hold in the subthreshold, transition, and strong inversion regions. A continuous model is proposed for the transition region, using a scheme that ensures that both the current and conductance are continuous and will not cause convergence problems for circuit simulation applications. All of the modeled parameters are taken from experimentally measured I-V characteristics and preserve physical meaning. Comparisons between the measured and modeled I-V characteristics show excellent agreement for a wide range of channel widths and biases. The model is well suited for circuit simulation in SPICE     

Submicrometer self-aligned AlGaAs/GaAs heterojunction bipolartransistor process suitable for digital applications

A self-aligned process is developed to obtain submicrometer high-performance AlGaAs/GaAs heterojunction bipolar transistors (HBTs) which can maintain a high current gain for emitter sizes on the order of 1 μm². The major features of the process are incorporation of an AlGaAs surface passivation structure around the entire emitter-base junction periphery to reduce surface recombination and reliable removal of base metal (Ti/W) deposits from the sidewall by electron cyclotron resonance (ECR) plasma deposition of oxide and ECR plasma etching by NF₃. A DC current gain of more than 30 can be obtained for HBTs with an emitter-base junction area of 0.5×2 μm² at submilliampere collector currents. The maximum f_T and f_max obtained from a 0.5×2 μm² emitter HBT are 46 and 42 GHz, respectively at I_C=1.5 and more than 20 GHz even at I_C=0.1 mA     

Si/a-Si:H heterojunction microwave bipolar transistors with cut-offfrequencies ft above 5 GHz

The fabrication of a silicon heterojunction microwave bipolar transistor with an n⁺ a-Si:H emitter is discussed, and experimental results are given. The device provides a base sheet resistance of 2 kΩ/□ a base width 0.1 μm, a maximum current gain of 21 (V_CE=6 V, I_c=15 mA), and an emitter Gummel number G _E of about 1.4×10¹⁴ Scm^-4. From the measured S parameters, a cutoff frequency f_t of 5.5 GHz and maximum oscillating frequency f_max of 7.5 GHz at V_CE=10 V, I_c=10 mA are obtained