Parameter extraction from I-V characteristics ofsingle MOSFETs

A method is presented to extract the bias-dependent series resistances and intrinsic conductance factor of individual MOS transistors from measured I-V characteristics. If applied to groups of scaled channel length devices, it also allows determination of the effective channel length together with the transversal field dependence of the carrier mobility. The method is exactly derived from conventional MOS theory based on the gradual channel approximation, and the deviations from such an ideal case are studied by means of two-dimensional device simulations. Experimental results obtained with n- and p-channel transistors of conventional as well as LDD type are presented to show the correctness of the proposed extraction procedure     

A complete model of the I-V characteristics fornarrow-gate MOSFETs

A unified and process-independent MOSFET model for accurate prediction of the I-V characteristics and the threshold voltages of narrow-gate MOSFETs is discussed. It is based on several enhancements of the SPICE2 LEVEL3 MOS model and the author's previous subthreshold I-V model. The expressions achieved for the drain current hold in the subthreshold, transition, and strong inversion regions. A continuous model is proposed for the transition region, using a scheme that ensures that both the current and conductance are continuous and will not cause convergence problems for circuit simulation applications. All of the modeled parameters are taken from experimentally measured I-V characteristics and preserve physical meaning. Comparisons between the measured and modeled I-V characteristics show excellent agreement for a wide range of channel widths and biases. The model is well suited for circuit simulation in SPICE     

Near-ideal I-V characteristics of GaInP/GaAsheterojunction bipolar transistors

GaInP/GaAs heterojunction bipolar transistors (HBTs) have been fabricated and these devices exhibit near-ideal I-V characteristics with very small magnitudes of the base-emitter junction space-charge recombination current. Measured current gains in both 6-μm×6-μm and 100-μm×100-μm devices remain constant for five decades of collector current and are greater than unity at ultrasmall current densities on the order of 1×10^-6 A/cm². For the 6-μm×6-μm device, the current gain reaches a high value of 190 at higher current levels. These device characteristics are also compared to published data of an abrupt AlGaAs/GaAs HBT having a base layer with similar doping level and thickness     

Input I-V and sampling time characteristics ofthe ACT device

The input I-V and sampling-time characteristics of the acoustic charge transport (ACT) device are presented for ohmic-contact charge injection and Schottky-gate-modulated charge injection. A computationally efficient analysis technique is developed to calculate the I-V and sampling-time data from two-dimensional potential and carrier-density distributions. Device physics and architecture are incorporated into the analysis through a numerical charge-injection model which is used to compute the potential and carrier-density distributions. Theoretical results are presented to demonstrate the charge injection characteristic of some typical device structures. The effects that the injection method, the epitaxial layer structure and the acoustic wave amplitude have on device performances are discussed. The physical basis of the analysis enables it to be used to study several other design parameters. Experimental measurements of a device I-V and input transconductance show good agreement with calculated data. This analysis technique provides a means of assessing the performance potential of new device designs     

A new I-V model for short gate-length MESFET's

An I-V model for short gate-length MESFETs operated in the turn-on region is proposed, in which the two-dimensional potential distributions contributed by the depletion-layer charges under the gate and in the ungated region are separately obtained by conventional 1-D approximation and the Green's function solution technique. Moreover, the bias-dependent parasitic resistances due to the modulation of the depletion layer in the ungated region for non-self-alignment MESFETs are also taken into account in the developed I-V model. It is shown that good agreement is obtained between the I-V model and the results of 2-D numerical analysis. Moreover, comparisons between the proposed analytical model and the experimental data are made, and excellent agreement is obtained     

Analytical model for I-V characteristics ofion-implanted MESFET's with heavily doped channel

A theoretical model for the I-V characteristics of ion-implanted metal-semiconductor field-effect transistors (MESFETs) has been developed. A formula for effective drift saturation velocity for electrons and a Gaussian approximation for the inverse of reduced distances in the channel have erased the process of formulation. Theoretical formulas for early saturation of drain current and transconductance obtained in the framework of the Lehovec-Zuleeg procedure are quite simple and accurate. When calculated results from the present model are compared with available experimental results, an encouraging correspondence between the two is observed. A study of the appropriateness of the velocity overshoot and the softening of pinch-off voltage indicates that both of these phenomena are real in short-channel MESFETs and need to be carefully accounted for in a realistic model. The model is equally applicable also to ion-implanted JFETs     

Dynamic I-V characteristics of anAlGaAs/GaAs-based optothyristor for pulsed power-switching applications

A high-performance MBE-grown AlGaAs/GaAs-based heterostructure optothyristor has been fabricated and characterized for high-power pulsed switching applications. An LEC undoped semi-insulating GaAs of 650 μm in thickness was used as the voltage blocking layer and low-temperature GaAs grown at 200°C was used to passivate the surface and to reduce the surface leakage current. The dynamic current-voltage characteristics have been measured up to 115 A and 1974 V, which corresponds to a field intensity of more than 30 kV/cm. The dissipated energy per switching as a function of device voltage has also been determined to be in the range of 2 mJ or lower     

Determination of device structure from GaAs/AlGaAs HEMT DC I-V characteristic curves

A procedure for the inverse modeling of GaAs/AlGaAs HEMT structures from the DC I-V characteristic is described. The procedure allows important structural parameters, including the aluminum fraction, dopant density, doped layer thickness, spacer layer thickness, physical gate length, source resistance, drain resistance, and the saturated electron velocity, in the 2DEG and in the doped AlGaAs to be obtained. The accuracy of the inverse modeling procedure is established by comparison of the derived HEMT structure with experimental results     

Modeling temperature effects in the DC I-Vcharacteristics of GaAs MESFET's

A simple model is presented to account for the main temperature effects influencing the DC performance of GaAs MESFETs. The model is based on a consistent solution of heat flow and current equations that accounts for nonuniform power dissipation within the device. The simulation results are satisfactorily compared with experimental data obtained with pulsed and DC measurements performed on conventional devices as well as on suitable test structures     

An analytical model for I-V and small-signalcharacteristics of planar-doped HEMTs

An analytical current-voltage (I-V) model for planar-doped HEMTs is developed. This compact model covers the complete range of I-V characteristics, including the current saturation region and parasitic conduction in the electron-supplying layer. Analytical expressions for the small-signal parameters and current-gain cutoff frequency are derived from the I-V model. Modeling results for a 0.1-μm-gate planar-doped AlInAs-GaInAs HEMT show excellent agreement with measured characteristics. Threshold voltages and parasitic conduction in planar-doped and uniformly doped HEMTs are also compared and discussed     

Influence of MOSFET I-V characteristics onswitching delay time of CMOS inverters after hot-carriers stress

The relationship between hot-carrier degradation in MOSFETs and CMOS inverters is studied. It is found that the device degradation characterized as the widely used bias points correlates poorly with the inverter degradation. The use of new bias points that are more meaningful for circuit performance is proposed. A simple equation for calculating the degradation of the propagation delay is developed     

Nonlinear parasitics in MODFETs and MODFET I-Vcharacteristics

A large-signal analysis of the source and drain resistance of MODFETs is reported. Velocity saturation in the two-dimensional electron gas (2DEG) and hypothetical rectifying effects in the n⁺-AlGaAs-i-GaAs interface are accounted for. Rectifying effects are found to be either absent or negligible. Current limitations in the 2DEG lead to the observed compression of the transconductance at large gate voltages, and an improved fit of the MODFET I-V characteristics is demonstrated using an approximate analytic formulation of the current-limited parasitic resistance. The high-frequency dependence of the source and drain resistance is also reported. A decrease of the source impedance for frequencies increasing from 1-30 GHz is predicted and can reach 30%, depending on the device structure. Such a frequency decrease of the parasitics is consistent with the reported increase of the effective transconductance of MODFETs at microwave frequencies. The reported frequency and current-limited parasitic models rely on parameters that can either be measured or calculated and are therefore appropriate for CAD applications     

Investigation of SOI-like I-V characteristics fora 64-Mb DRAM SCC MOSFET with a buried drain

The MOSFET structure of a surrounding-high-capacitance cell (SCC) trench cell with a buried drain scaled down for 64-Mb DRAM applications has been studied using the device simulator MINIMOS. For this cell design, the depletion zones of the buried drain can pinch off the substrate at a sufficiently high drain bias. The resulting floating substrate causes sharply increased avalanche carrier generation similar to (but more severe than) the kink effects found in SOI structures. These effects limit the utility of this structure for small-geometry DRAM structures. The mechanism for the enhanced avalanche generation and its dependence on bias conditions and geometry have been studied, and pertinent design rules for punchthrough and pinchoff by the buried drain have been established     

Modeling of nonhyperbolic sine I-Vcharacteristics in poly-Si resistors

Poly-Si resistors with an unimplanted channel region (and with n-type source/drain regions) can exhibit a nonhyperbolic sine (non-sinh) I-V characteristic at low V_DS and an activation energy which is not simply decreasing monotonically with increasing V_DS. These phenomena are not explained by conventional poly-Si resistor models. To describe these characteristics, a self-consistent model which includes the effects of a reverse-biased diode at the drain end is presented. Numerical simulation results show excellent agreement with experiment in regard to the shape of the I -V characteristic and of the effective activation energy as a function of V_DS     

SPICE macro model for the simulation of zener diodeI-V characteristics

The problems encountered when using the existing SPICE diode model to represent the I-V characteristics of a Zener diode in the reverse region are examined. A Zener diode macro model that has accurate I-V simulation characteristics and can be easily constructed using SPICE-provided primitives is presented. The static I-V characteristics and temperature response of the diode are reviewed. The performance of the model is discussed, and its main enhancements as compared to the SPICE model are identified     

Electrochemical C-V profiling of heterojunctiondevice structures

Electrochemical capacitance-voltage profiles of multiple (In,Al) GaAs heterostructures have been measured and compared with the results of a numerical calculation of the apparent charge density based on a one-dimensional Poisson solver. The calculation, using layer thicknesses, dopings, and heterojunction band discontinuities obtained from MBE growth calibrations, is in overall agreement with the measured data. The largest discrepancy occurs between the expected and measured heterojunction band discontinuity. This difference is consistent with an electrolyte/semiconductor interface which is not planar on a scale comparable to the layer thickness     

Analysis of negative differential resistance in theI-V characteristics of shorted-anode LIGBT's

The physical mechanism responsible for the negative differential resistance (NDR) in the current-voltage characteristics of the shorted anode lateral insulated gate bipolar transistor (SA-LIGBT) is explained through two-dimensional numerical simulation. The NDR regime is an inherent feature of all SA-LIGBTs, and results from the two different conduction mechanisms responsible for current flow in the device. These conduction mechanisms are minority-carrier injection and majority-carrier flow. Since both the anode geometry and the doping profile control the onset and the degree of minority-carrier injection, the effect these parameters have on the NDR is investigated. A simple lumped-element equivalent model of the SA-LIGBT allows qualitative predictions to be made on how changes in the device geometry and doping profiles influence the NDR regime. It is shown that conductivity modulation is a necessary but not sufficient condition for the occurrence of negative resistance in SA-LIGBT devices. Also required is a large voltage drop in the high-resistivity drift region before conductivity modulation is initiated. This causes small changes in the anode current level, greatly decreasing the total resistance across the drift region     

Modeling the gate I/V characteristic of a GaAsMESFET for Volterra-series analysis

The authors show that the Taylor-series coefficients of a FET's gate/drain I/V characteristic, which is used to model this nonlinearity for Volterra-series analysis, can be derived from low-frequency RF measurements of harmonic output levels. The method circumvents many of the problems encountered in using DC measurements to characterize this nonlinearity. This method was used to determine the incremental gate I/V characteristic of a packaged Aventek AT10650-5 MESFET biased at a drain voltage of 3 V and drain current of 20 mA. The FET's transconductance was measured at DC, and its small-signal equivalent circuit (including the package parasitics) was determined by adjusting its circuit element values until good agreement between calculated and measured S parameters was obtained. The FET was then installed in a low-frequency test fixture. Excellent results were obtained     

Temperature dependence of common-emitter I-V andcollector breakdown voltage characteristics in AlGaAs/GaAs andAlInAs/GaInAs HBT's grown by MBE

Temperature-dependent measurements from 25 to 125°C have been made of the DC I-V characteristics of HBTs with GaAs and In_0.53Ga_0.47As collector regions. It was found that the GaAs HBTs have very low output conductance and high collector breakdown voltage BV_CEO>10 V at 25°C, which increases with temperature. In striking contrast, the In_0.53Ga_0.47As HBTs have very high output conductance and low BV_CEO~2.5 V at 25°C, which actually decreases with temperature. This different behavior is explained by the >10⁴ higher collector leakage current, I_CO, in In_0.53Ga_0.47As compared to GaAs due to bandgap differences. It is also shown that device self-heating plays a role in the I-V characteristics     

Comparison of I-V, CV, and chemical datafor quality control studies of SiOxNy films on Si

Capacitance-voltage (CV) and current-voltage (I- V) measurements for SiO_xN_y films are compared with chemical data in order to provide some diagnostic capabilities in relating aberrant electrical characteristics with contaminants incorporated in the insulator film structure. In-process monitoring of film quality (utilizing electrical characteristics and chemical data) is especially critical in very large-scale integration (VLSI) processing control where the films are utilized both as an integral part of specific semiconductor device processing steps or as part of the semiconductor device structure