新的浮点处理器能直接进行对数运算

嵌入式系统设计的复杂趋势是由于模拟电路、高速数字电路和射频电路等共存于同一电路中而造成的。针对用户进行混合信号调试方面的需求。安捷伦公司推出了新型数字存储示波器(DSO)和混合信号示波器(MSO)Infiniium 8000系列,包括600MHz     

溶胶-凝胶法制备铜掺杂氧化锌薄膜的光学特性

设计了一种新的能量回收接口电路——双中间电容回收(DICH)接口电路,该电路由2个LC振荡电路、一个buck boost转换器和2个中间电容组成。完成了在恒定激振位移情况下该电路的回收功率的理论分析和计算。利用Multisim仿真软件对标准电路、同步电荷提取(SECE)接口电路、并联 同步开关电感回收 (SSHI)、串联 SSHI和DICH接口电路进行了仿真比较,结果表明,双中间电容回收(DICH)接口电路在最优负载时的最大回收功率仅小于并联 SSHI接口电路,约是SECE接口电路的2倍,且具有与SECE接口电路同样的特性,即回收功率与负载无关。     

DICH压电能量回收接口电路设计

设计了一种新的能量回收接口电路——双中间电容回收(DICH)接口电路,该电路由2个LC振荡电路、一个buck-boost转换器和2个中间电容组成。完成了在恒定激振位移情况下该电路的回收功率的理论分析和计算。利用Multisim仿真软件对标准电路、同步电荷提取(SECE)接口电路、并联-同步开关电感回收(SSHI)、串联-SSHI和DICH接口电路进行了仿真比较,结果表明,双中间电容回收(DICH)接口电路在最优负载时的最大回收功率仅小于并联-SSHI接口电路,约是SECE接口电路的2倍,且具有与SECE接口电路同样的特性,即回收功率与负载无关。     

SCEI能量回收接口电路的设计

基于压电效应的能量回收接口电路是能量回收系统的重要组成部分,经典的接口电路有标准接口、同步电荷提取电路(SECE)、并联同步开关电感电路(Parallel-SSHI)、串联同步开关电感电路(Series-SSHI)4种。提出并设计了一种新的接口电路——同步电荷提取和翻转电路(SCEI)接口电路,完成了该接口电路在恒定激振位移情况下回收功率的理论分析和计算,并利用电子仿真软件Multisim对SCEI和4种典型接口电路的回收功率进行了仿真和比较。结果表明,SCEI接口电路性能优越,其回收功率约是SECE电路的1.5倍,且与负载无关。     

程控交换机专用接口电路的技术创新

程控交换机专用接口电路是上海贝岭公司拥有多项知识产权的大规模集成电路产品。本文以CSLIC电路(中国版用户接口电路)为例，详细介绍了上海贝岭公司在这种产品的设计、工艺、封装和工程分析等多个领域的技术创新成果。     

系统控制电路及其各方案比较

前面的文章我们已介绍了数字机的绝大部分电路，其实仅有电路还是不行的，这些电路如何工作，人们又如何去操作它，这就需要有一套控制电路。由主CPU、程序存储器(EPROM或FLASH)、数据存储器(DRAM、SDRAM)、总线驱动器和各种接口电路组成的控制电路，是数字机的控制中心。其主要作用是控制和协调各部分电路的工作，完成整机系统的初始化和测试、安全处理、通讯口协议处理及PSI表的管理等任务。按照设计的程序完成机器的各种功能，以及通过操作面板接口和IR遥控器接口与使用者进行人机对话。     

应用于红外读出电路的LVDS接收电路设计

在大规模红外读出电路中,接口电路的数据传输效率及接口数量尤为关键。传统接口电路采用并行接口进行数据传输,这种方式会占用较多的芯片引脚。为了提升数据的传输效率,设计了一款用于数据接收的3通道串行低压差分信号(Low Voltage Differential Signaling, LVDS)接口电路。电路采用0.18um互补金属氧化物半导体(Complementary Metal Oxide Semiconductor, CMOS)工艺设计。仿真结果表明,LVDS接口电路在400 MHz频率下,能够将2路接收端数据转换为8路数据并将其输出给内部数字处理单元。与传统并行接口相比,本电路节省了6个数据传输引脚,大大提高了数据传输效率。     

单片机外围接口电路

<正> 外围接口电路的原理 1.为什么要扩展外围接口电路? 单片机芯片已经具有了计算机的全部功能,也就是说,如果在最小系统下,一片单片机芯片接入少许外围电路(晶体振荡器、复位电路)就可以正常工作了。但是,在实际应用中,最小系统往往不能满足需要,通常会出现以下几种情况:(1)接口数不够。单片机的输出、输入接口数量不多,例如8031只有一个独立的8位口(P1口),89C2051也只有15条线可以作为接口,在许多情况下是不能满足需要的,这时就需要扩展接口电路;(2)部件量不够。单片机内部虽然已经具有计算机的主要     

一种DSO专用的LCD驱动器设计

为适应数字存储示波器DSO(Digital Storage Oscilloscope)对动态波形显示的需要，讨论了一种不使用专门的液晶显示器LCD(Liquid Crystal Display)驱动芯片而直接采用数字信号处理器DSP(Digital Signal Processor)产生LCD的帧扫描、行扫描以及数据信号，从而实现对LCD驱动的方法。该驱动器能显著提高DSO波形的显示速度并在某些型号的数字示波器中得到成功应用。     

RS—232接口电路的ESD保护

RS-232接口标准是由电子工业协会(EIA)和电信工业协会(TIA)制定的,已广泛应用于低速短距离的计算机终端和外设之间的连接。RS-232标准规定正负电源代表逻辑0和1,而计算机和终端内部的高低电平来表示逻辑状态,所以需要RS-232接口电路提供电平转换。RS-232接口电路的关键特性包括可靠性,低功耗和ESD保护。MAXIM公司最早将自动关断功能引入RS-232接口电路,把静态功耗降低到1μA,1994年首创带有±15KV静电保护(ESD)的RS-232接口电路,随后将这种ESD保护结构应用在3V供电的RS-232接口电路中。在接口电路方面MAXIM处于业内领先地位,所生产的接口器件具备高可靠性和高品质。下面介绍MAXIM公司在ESD保护方面的特殊优势和产品。     

通过LAN在计算机屏幕上控制DSO6104L实现测量

本文就通过DSO6104L示波器的LAN接口实现网络控制问题,介绍了LAN Non-Auto-MDIX接口含义、计算机与DSO6104L的相连注意事项、LAN参数设置方法及充分利用其内部提供的远程前面板接口功能,通过Web浏览器实现控制类似于真实示波器仪器,不需要编写任何程序就可以达到远程控制的目的,该方法利用了仪器固有的资源,避免了资源浪费和无形的损失,可以直接利用其功能组建分布式测试系统,避免了程序设计和繁琐调试过程,对程序设计者和使用者具有很高的参考借鉴价值。     

一种2Gsps数字示波器数据采集系统的设计

数据采集系统是数字存储示波器的核心部分。在研究剖析数字存储示波器工作原理的基础上,围绕其数字系统的设计与实现,采用ADC＋高频时钟电路＋FPGA＋DSP的结构模式,实现最高实时采样率2Gsps、分辨力8bit、存储深度8MB／CH的示波器数据采集系统,为国内高速数据采集系统设计提供了一种解决方案。     

Power line filter design for conducted electromagnetic interference using time-domain measurements

A time-domain technique for the design of passive power line conducted electromagnetic interference (EMI) filters in the frequency range 150 kHz-30 MHz is described. A digital storage oscilloscope (DSO) with adequate sampling, storing and processing features is sufficient for the design using the proposed technique. Accordingly, Agilent's Infiniium Oscilloscope (Model 54810A) has been used. The signals from LISN are directly fed into the two channels of the DSO where they are added and subtracted to separate the CM and DM components, thereby eliminating the need for common-mode-differential mode (CM-DM) separator. These components are stored in the DSO. A specially designed filter design software (FDS), residing in the DSO, estimates the noise spectrum by computing the Bartlett and Welch periodograms. It also computes the filter component values. Thus, the sampling of the conducted noise, separation of CM and DM components, signal processing, and filter value computations are all done using one DSO. A spectrum analyzer is not required. Bartlett periodograms have been preferred over Welch periodograms due to low memory storage requirements of the former. The proposed technique has been applied to the design of power line filter for a switched mode power supply (SMPS), and satisfactory results have been obtained. The proposed measurement scheme is compact, economical, and convenient. All the details of this work are presented.     

Dual symbol optimization‐based partial transmit sequence technique for PAPR reduction in WOLA‐OFDM waveform

Weighted overlap and add‐orthogonal frequency division multiplexing (WOLA‐OFDM) is a new waveform proposed recently for meeting the requirements of fifth generation (5G) telecommunication standards. In spite of being a serious 5G waveform candidate, WOLA‐OFDM is exposed to the problem of high peak to average power ratio (PAPR) similar to the other waveforms in which multicarrier transmission strategy is employed. Due to the overlapping nature of WOLA‐OFDM waveform, where the extension of the current symbol is overlapped with the extension of the previous symbol, it will not be efficient to apply conventional PTS (C‐PTS) directly to the WOLA‐OFDM waveform. Therefore, in this paper, we propose dual symbol optimization‐based partial transmit sequence (DSO‐PTS) technique for PAPR reduction in WOLA‐OFDM waveform. In our proposed technique, two adjacent symbols are jointly considered when searching for the optimal data block with minimum PAPR unlike the C‐PTS where the adjacent symbols are optimized individually. In the simulations, our proposed DSO‐PTS technique, C‐PTS, and GreenOFDM that is developed recently by modifying the conventional selective mapping (SLM) method are compared with each other with regard to PAPR reduction performance for different search numbers (SNs). In addition, the effects of DSO‐PTS, C‐PTS, and GreenOFDM on the amount of out of band (OOB) radiation in the power spectral density (PSD) graph of WOLA‐OFDM employing solid state power amplifier (SSPA) is measured for different SNs and input back off (IBO) values. According to the simulation results, our proposed DSO‐PTS technique clearly demonstrates a superior PAPR reduction and PSD performance.     

微悬臂谐振传感器闭环接口和嵌入式频率电路

设计了谐振式微悬臂梁传感器闭环接口和嵌入式频率读出电路。首先,谐振式微悬臂梁传感器和接口电路组成闭环自激振荡系统。为了提高该闭环系统的频率稳定性和频率跟踪性能,引入具有无相差频率跟踪的锁相环电路,并设计放大移相电路以满足闭环自激振荡条件。该闭环系统的频率稳定性可达±0.1Hz,并且能够实时跟踪悬臂梁谐振频率的变化。此外,单独设计了嵌入式的频率读出电路,用于检测并显示悬臂梁的谐振频率。将悬臂梁传感器、接口电路和频率读出电路集成在一起,做出了小巧便携式样机,用该样机可成功探测到体积分数低至约几个10-9量级的DMMP气体。     

Interface circuit synthesis of system-on-chip

Most of the intellectual properties (IPs) of system-on-chip (SoC) are provided by different vendors, and thus they may have various characteristics, making the interface circuit synthesis of SoC a time-consuming and error-prone process. The main contribution of this article is to present an interface synthesis algorithm for power minimisation in interface circuit design of SoC. Moreover, we also study the power and area trade-off in interface circuit synthesis of such systems. By starting from the power-minimal solution, we perform a sequence of power relaxation operations and area-minimising procedures to produce a set of solutions for a given SoC interface circuit design with power and area trade-off considerations. The experimental results demonstrate the effectiveness of our algorithms.     

A Hot-Swap Solution for Paralleled Power Modules by Using Current-Sharing Interface Circuits

A hot swap of power modules is required by high-availability parallel power module systems. With the hot-swappable paralleled power modules, the system up-time can be maximized, the system maintenance and repair can be simplified, and the system upgrade can be allowed for. In this paper, a simple hot-swap solution is proposed for the paralleled power modules which use current-sharing (CS) interface circuits to do the CS work. By redesigning the basic function circuits of the CS interface circuits (such as the under voltage protection circuit, the current-sharing circuit, and the light load protection circuit etc.), an additional hot-swap function can be implemented "parasitically". There is no extra hot-swap controller and no compatibility problem between the hot-swap and CS solutions used. A prototype CS interface circuit with a "parasitic" hot-swap function was designed, implemented, and tested. The results show that the proposed hot-swap solution is feasible and suitable     

基于光电检测技术的电缆材料缺陷检测系统

采用在测量上广泛使用的光电转换器件线阵CCD技术,完成了电缆材料缺陷检测系统的总体方案设计。基于DSO的电缆材料缺陷检测系统在平行光的照射下,通过线阵CCD控制电路获得电缆材料缺陷信号,使用虚拟示波器DSO-2902对一维缺陷信号进行采集、传输,借助于计算机进行分析处理,从而精准地检测出缺陷。     

基于SRAM和FPGA的DSO深存储功能设计

存储深度决定了数字存储示波器能够连续采集信号的最大时长,也决定了示波器在各个时基档位的实时采样率,提高存储深度有助于提高示波器的连续捕获时间和实时采样率。文章采用SRAM进行数据存储,利用FPC．A接收采样率为1Gsps的ADC的采样数据及控制SRAM的读写等,实现了采样率为1Gsps、存储深度为IM的深存储功能设计。