Current progress in modeling self-heating effects in FD SOI devices and nanowire transistors

In this paper we summarize 6 years of work on modeling self-heating effects in nano-scale devices at Arizona State University (ASU). We first describe the key features of the electro-thermal Monte Carlo device simulator (the two-dimensional and the three-dimensional version of the tool) and then we present series of representative simulation results that clearly illustrate the importance of self-heating in larger nanoscale devices made in silicon on insulator technology (SOI). Our simulation results also show that in the smallest devices considered the heat is in the contacts, not in the active channel region of the device. Therefore, integrated circuits get hotter due to larger density of devices but the device performance is only slightly degraded at the smallest device size. This is because of two factors: pronounced velocity overshoot effect and smaller thermal resistance of the buried oxide layer. Efficient removal of heat from the metal contacts is still an unsolved problem and can lead to a variety of non-desirable effects, including electromigration. We propose ways how heat can be effectively removed from the device by using silicon on diamond and silicon on AlN technologies. We also study the interplay of Coulomb interactions due to the presence of a random trap at the source end of the channel and the self-heating effects. We illustrate the influence of a positive and a negative trap on the magnitude of the on-current and the role of the potential barrier at the source end of the channel.     

The importance of thermal conductivity modeling for simulations of self-heating effects in FD SOI devices

In this review paper we want to emphasize the importance of having accurate thermal conductivity models for modeling self-heating effects on the device level. For that purpose, we first consider thin silicon films and calculate (using Sondheimer’s approach) their thermal conductivity that incorporates boundary scattering. We then compare the obtained thermal conductivity data with experimental measurements to prove the excellent model agreement with the experimental trends. The parameterized thermal conductivity data are then used in the higher level modeling of self-heating effects in fully-depleted (FD) SOI devices from different technology generations. We find that temperature and thickness dependent modeling of the thermal conductivity is essential for the 25 nanometers technology node. We have also taken into account the anisotropy of the thermal conductivity and modeled devices with (100) and (110) crystallographic orientation. We found out that from thermal point of view the (110) device behaves better, but the (100) device has higher on-current.     

Study of Electron Transport in SOI MOSFETs Using Monte Carlo Technique with Full-Band Modeling

Effects of conduction-band non-parabolicity on electron transport properties in silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs) are studied by performing Monte Carlo simulation with a full-band modeling. An empirical pseudo-potential method is adopted for evaluating the two-dimensional electronic states in SOI MOSFETs. SOI-film thickness dependence of phonon-limited mobility, drift-velocity and subband occupancy is calculated and the results are compared with those of a simple effective mass approximation. The non-parabolicity effects are found to play an important role in 4-fold valleys under higher applied electric fields or at higher temperatures.     

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.     

Study of performance and leakage currents in nanometer-scale bulk,SOI and double-gate MOSFETs

We consider the performance and leakage issues in 80-to-20 nm Ge, Si, and InGaAs bulk, SOI and Double-gate (DG) devices. The performance is studied with DAMOCLES, band-to-band tunneling processes with a nonlocal band-to-band model as a post-processor in DAMOCLES, and gate tunneling by a Green’s function method accounting also for image force effects, so far ignored at ‘internal’ interfaces. The performance is affected by the bottleneck effect in III–Vs, especially for thin channels, but InGaAs and Ge still may be optimized to outperform Si. Zener leakage is high for Ge and tolerable for InGaAs. The effect of image forces led to an order of magnitude increase in gate tunneling currents.     

Analytical modeling of subthreshold swing in undoped trigate SOI MOSFETs

A new analytical model for the subthreshold swing of nanoscale undoped trigate silicon-on-insulator metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed, based on the channel potential distribution and physical conduction path concept. An analytical model for the potential distribution is obtained by solving the three-dimensional (3-D) Poisson’s equation, assuming a parabolic potential distribution between the lateral gates. In addition, mobile charges are considered in the model. The proposed analytical model is investigated and compared with results obtained from 3-D simulations using the ATLAS device simulator and experimental data. It is demonstrated that the analytical model predicts the subthreshold swing with good accuracy for different lengthes, thicknesses, and widths of channel.     

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.     

Full-Band Monte Carlo Simulation of Two-Dimensional Electron Gas in SOI MOSFETs

A full-band Monte Carlo simulation of two-dimensional electron gas is performed to study effects of the non-parabolicity of the energy band structure on the phonon-limited electron mobility in SOI MOSFETs with a thin Si-layer.     

2D Modeling of nanoscale DG SOI MOSFETs in and near the subthreshold regime

We have developed a 2D model for double-gate SOI MOSFET based on a solution of the Laplacian for the device body utilizing conformal mapping techniques. The model yields explicit expressions for the subthreshold and near-threshold electrostatics of the device, including the perpendicular electrical field and the potential distributions along the silicon/insulator interfaces and at the center gate-to-gate axis. From these expressions, we derive information on the threshold conditions, the potential barrier topography, and the electron density distribution in the device under different biasing conditions. This model constitutes a framework for very precise, scalable, compact models of nanoscale MOSFETs.     

LET-dependent model of single-event effects in MOSFETs

In this paper, we simulate the electrical characteristics of the n-type metal-oxide-semiconductor (NMOS) transistor in a 65-nm complementary metal-oxide-semiconductor (CMOS) inverter under the actions of heavy ions with different linear energy transfers (LET). We analyze the influence of incident ions with different LETs on a device using technology computer-aided design (TCAD) software, and aim to establish an HSPICE sub-circuit model containing the relationship between the electrical properties of a device and the LET of an incident ion for circuit-level HSPICE simulation. Based on the SEE funnel mechanism, we propose an analytical model to describe the relationship between the charge collected by the NMOS drain and the LET of the incident ion, and build an HSPICE model based on this analytical model. With such a model, the influence of incident ions with different circuit-level LETs can be determined from HSPICE simulation. In addition, good agreement with simulation results is reached, proving the reasonableness of the proposed model.

     

3D Monte Carlo Modeling of Thin SOI MOSFETs Including the Effective Potential and Random Dopant Distribution

We use the effective potential to include quantum mechanical effects in thin SOI MOSFETs simulated with 3D Monte Carlo. We explore the role of discrete dopant distributions on the threshold voltage of the device within the framework of the effective potential by examining the current-voltage behavior as well as the electron distributions within the device. We find that simulations with the effective potential produce a similar shift in current as classical simulations when the dopants are considered to have a random discrete distribution instead of a uniform distribution.     

不同封装形式压接型IGBT器件的电-热应力研究

基于多物理场建模对比分析全压接和银烧结封装压接型IGBT器件的电-热应力。首先根据全压接和银烧结封装压接型IGBT的实际结构和材料属性,建立3.3 kV/50 A压接型IGBT器件的电-热-力多耦合场有限元模型;其次仿真分析额定工况下2种封装IGBT器件的电-热性能,并通过实验平台验证所建模型的合理性;然后研究了3.3 kV/1 500 A多芯片压接型IGBT模块的电-热应力,并探究了不同封装压接型IGBT器件电-热应力存在差异的原因;最后比较了2种封装压接型IGBT器件内部的电-热应力随夹具压力和导通电流变化的规律。结果表明银烧结封装降低了压接型IGBT器件的导通压降和结温,提升了器件散热能力;但银烧结封装也增大了IGBT芯片表面的机械应力,应力增大对IGBT器件疲劳失效的影响亟需实验验证。     

The Role of Quantization Effects on the Operation of 50 nm MOSFETs, 250 nm FIBMOS Devices and Narrow-Width SOI Device Structures

We investigate the role of the quantum-mechanical space-quantization effects on the operation of a 50 nm MOSFET device, an asymmetric 250 nm FIBMOS device and a narrow-width SOI device structure. We find that space-quantization effects give rise to larger average displacement of the carriers from the interface proper and lower sheet electron density in both the regular and the asymmetric MOSFET device structures. The effect is even more pronounced in the narrow-width SOI device due to the presence of a two-dimensional confinement (both vertical and along the width direction). The reduction in the sheet electron density, in turn, gives rise to shift in the devices threshold voltage, on the order of 100–200 mV, depending upon the device structure being investigated. This leads to 20–40% decrease of the device on-state current which depends upon the gate bias. Hence, to properly describe the operation of future ultra-small devices it is mandatory to incorporate quantum-mechanical space quantization effects into existing classical device simulators (drift-diffusion, hydrodynamics or Monte Carlo particle-based simulators) since first-principle quantum-mechanical calculations (direct solution of the many-body Schrödinger equation, Green's functions method, etc.) are still limited to one-dimensional structures and rely on a number of approximations.     

备自投含风电时和常规能源不同备自投的考虑

针对传统备自投在发展中遇到的一些问题,提出构建区域备自投系统的构想.论述了有源同期并列非同期问题.备自投动作成功时运行设备存在过载问题和串供多个变电站时线路备自投无法保证所有变电站不失压问题、母线故障备自投误动以及备自投合风电时等情况,并根据区域备自投系统构想提出改进建议,分析表明:所述几种情况均能得到有效解决,区域备自投构想对备自投未来的发展方向有一定指导意义.     

适用于电动汽车的SiC MOSFET PSpice仿真模型研究

为了基于PSpice电路对电动汽车DC/DC变换器中的碳化硅(SiC)MOSFET的工作特性进行实时准确地仿真,针对SiC MOSFET提出了一种新型的电压控制电流源型VCCST(voltage-controlled current source type)PSpice仿真模型。首先,为了获得SiC MOSFET准确的静态特性建立了电压控制电流源作为SiC MOSFET的内核,以描述SiC MOSFET的转移特性和输出特性;然后,为了获得SiC MOSFET准确的动态特性,建立了基于电压控制电流源与恒定电容的栅漏电容(CGD)子电路模型,所提SiC MOSFET VCCST PSpice模型在简化参数提取方法的同时,能够满足模型准确性的要求;最后,建立的SiC MOSFET VCCST PSpice模型应用于Boost变换器进行仿真和实验,并对SiC MOSFET的特性进行测试。测试结果验证了所提SiC MOSFET VCCST PSpice仿真模型的准确性和实时性,从而为SiC MOSFET在电动汽车DC/DC变换器中的设计和应用提供了便利。     

Study of RF Linearity in sub-50 nm MOSFETs Using Simulations

We investigate the linearity performance of dual-gate and fully-depleted silicon-on-insulator MOSFETs through use of 2D computer simulations, which take into account quantum mechanical considerations and non-equilibrium transport effects. We show that DG MOSFET is superior not only in terms of g _m /I _d characteristics, central to analog performance, but also in terms of linearity performance, by up to 5 dBm, in most operating conditions. Linearity figures of devices considered in this work range from ?10 to ?20 dBm, which answer the needs of mobile communication standards currently in use. We also observe that, when properly scaled, bulk MOSFETs display competitive analog performance and have third-order intercept figures very similar to SOI device. We can identify, through simulation experiments, that quantum mechanical effects have positive impact on linearity, while non-equilibrium conditions lower linearity performance. With increasing drain bias, we find that linearity saturates at a moderately low voltage (～1 V) in all devices.     

Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs

In this paper, analytical subthreshold current and subthreshold swing models are derived for the short-channel dual-metal-gate (DMG) fully-depleted (FD) recessed-source/ drain (Re-S/D) SOI MOSFETs considering that diffusion is the dominant current flow mechanism in subthreshold regime of the device operation. The two-dimensional (2D) channel potential is derived in terms of back surface potential and other device parameters. The so called virtual cathode potential in term of the minimum of back surface potential is also derived from 2D channel potential. The virtual cathode potential based subthreshold current and surface potential based subthreshold swing model results are extensively analyzed for various device parameters like the oxide and silicon thicknesses, thickness of source/drain extension in the BOX, control to screen gate length ratio and channel length. The numerical simulation results obtained from ATLAS \(^{\text{ TM }}\) , a 2D numerical device simulator from SILVACO Inc have been used as a tool to verify the model results.     

Comparison of Double-Gate MOSFETs and FinFETs with Monte Carlo Simulation

A full-band Monte Carlo simulator has been used to analyze and compare the performance of n-channel double-gate MOSFETs and FinFETs. Size quantization effects were accounted for by using a quantum correction based on Schrödinger equation. FinFETs are a variation of typical double-gate devices with the gate surrounding the channel on three sides. From our simulations, we observed that the quantization effects in double-gate devices are less significant as compared to bulk MOSFETs. The total sheet charge density drops only slightly as the depletion of charge at the interface is counterbalanced by the increased volume inversion effect. We also observed an appreciable drop in average velocity distribution when quantum corrections were applied. For FinFETs, the fin extension lengths on either side of the gate affect the device performance significantly. These underlap regions have low carrier concentration and behave as large resistors. The current drops non-linearly with increasing fin extension lengths.     

基于CPLD的船舶驾驶台模拟器设计研究

为了改进现有船舶驾驶台模拟设备的真实感不强、集成度不高以及数据传输效率低下问题,从软硬件两个方面提出了一种新的驾驶台模拟设备设计方案.硬件方面,以CPLD作为核心控制单元,设计了模拟设备驱动电路以及基于USB20D模块的高速数据传输通道;软件方面,以VS2010作为开发平台,利用USB20D模块自带的驱动模块,完成了上位机通信程序的设计.通过实验及实际操作可知,新的驾驶台模拟设备在外观及功能上与真实设备相仿,具有较强的沉浸感,同时对现有设备的扩展性能进行了增强.     

基于DSP控制的逆变电源装置的研究

介绍了基于高性能DSP的逆变电源全数字化控制方案,该方案结合了重复控制、预测PID控制和前馈控制的优点,能减小逆变电源在非线性周期负载下的输出电压谐波畸变率和阶跃负载时的超调量。通过对1.6kVA单相SPWM逆变电源实验装置的实验,实验结果显示所采用的全数字化控制方案能达到逆变电源在各种负载条件下的动态和稳态指标要求。