双层螺旋RF MEMS电感的模拟与设计

分析了双层螺旋电感的等效电路模型,研究了一种与传统CMOS工艺兼容的MEMS工艺,通过腐蚀电感结构下的硅衬底使电感悬空.利用HFSS软件对一些双层螺旋微电感进行了模拟,模拟结果表明,相比传统单层电感,双层电感可以减少60%的芯片面积,10nH的电感也只需要很小的面积,经过MEMS后处理的双层螺旋电感的最大Q值都超过了20.     

Equivalent Circuit Analysis of an RF Integrated Inductor with Ferrite Thin-Film

针对已制作并发表的一种新型铁氧体磁膜结构射频集成微电感进行了等效电路分析.阐述了磁性铁氧体薄膜对电感的感值(L)和品质因数(Q)的增强作用.对射频测试结果进行了电路元件参数提取.结果表明,与空气芯无磁膜微电感相比,磁膜结构微电感的L和Q在2GHz处分别提高了17%和40%.等效电路分析和测试结果均证明了铁氧体薄膜的引入对增强射频集成微电感性能的作用显著.     

铁氧体磁膜RF集成微电感等效电路分析

针对已制作并发表的一种新型铁氧体磁膜结构射频集成微电感进行了等效电路分析.阐述了磁性铁氧体薄膜对电感的感值(L)和品质因数(Q)的增强作用.对射频测试结果进行了电路元件参数提取.结果表明,与空气芯无磁膜微电感相比,磁膜结构微电感的L和Q在2GHz处分别提高了17%和40%.等效电路分析和测试结果均证明了铁氧体薄膜的引入对增强射频集成微电感性能的作用显著.     

Integrated Multilayered On-Chip Inductors for Compact CMOS RFICs and Their Use in a Miniature Distributed Low-Noise-Amplifier Design for Ultra-Wideband Applications

A novel multilayered vertically integrated inductor structure is developed for miniature CMOS RF integrated circuits, and its properties are investigated. The effect of mutual inductance both within and between adjacent multilayer inductors is also studied. A distributed low noise amplifier is designed by incorporating this novel inductor structure in a standard JAZZ 0.18-$mu$m RF/mixed signal CMOS process, demonstrating the significance of the proposed multilayered inductors in CMOS circuit miniaturization. The three-stage distributed amplifier occupies just 288$,times,$291 $mu$m or 0.08 mm $^{2}$ of die area, making it the smallest distributed amplifier reported to date. The circuit exhibits a relatively flat gain of 6 dB from 3.1 to 10.6 GHz with less than 0.5-dB ripple, with excellent input and output match of less than ${-}$ 12 and ${-}$25 dB, respectively. The noise figure is less than 5 dB to 14 GHz with only 2.7 dB across 8–10 GHz, while the power consumption is approximately 22 mW.      

PCB integrated inductors for low power DC/DC converter

This paper discusses the use of printed circuit board (PCB) integrated inductors for low power DC/DC buck converters. Coreless, magnetic plates and closed core structures are compared in terms of achievable inductance, power handling and efficiency in a footprint of 10 /spl times/ 10 mm/sup 2/. The magnetic layers consist of electroplated NiFe, so that the process is fully compatible with standard PCB process. Analytic and finite element method (FEM) methods are applied to predict inductor performance for typical current waveforms encountered in a buck converter. Conventional magnetic design procedures are applied to define optimum winding and core structures for typical inductor specifications. A 4.7 /spl mu/H PCB integrated inductor with dc current handling of up to 500 mA is presented. This inductor is employed in a 1.5 W buck converter using a commercial control integrated circuit (IC). The footprint of the entire converter measures 10 /spl times/ 10 mm/sup 2/ and is built on top of the integrated inductor to demonstrate the concept of integrated passives in power electronic circuits to achieve ultra flat and compact converter solutions.     

CMOS Micromachined Inductors With Structure Supports for RF Mixer Matching Networks

This letter presents the comparison of three novel structure supports for on-chip complementary metal–oxide–semiconductor (CMOS)-based micromachined inductors by using a proposed two-step maskless post-CMOS process. A 3-D electromagnetic inductor simulation model is established and calibrated with inductor fabrication. The proposed inductors are applied in the matching network of the double-balanced Gilbert mixer to improve the performance and the mechanical stability. The mixers, with and without micromachined process inductors, are fabricated in a 0.5-$muhbox{m}$ CMOS process and compared in this letter. The measurement results show a 28.12% increase in conversion gain, a 31.7% improvement in third intercept point, and a 44% reduction in the noise figure.      

On-chip solenoid inductors with high quality factor for high frequency magnetic integrated circuits

On-chip solenoid inductors for high frequency magnetic integrated circuits are proposed. The eddy current loss was reduced by dividing the inductor into three consecutive inductors connected in series. The inductor has an inductance of 1.1nH and the maximum quality factor (Q/sub max/) of 50.5. The self-resonant frequency and the operating frequency at Q/sub max/ are greater than 17.5GHz and 16.7GHz, respectively.     

A novel geometry for circular series connected multilevel inductorsfor CMOS RF integrated circuits

The scope of this brief is to introduce a novel geometry for circular series connected multilevel inductors. The idea is to improve the overlapping of the different metal layers that form the integrated inductor to maximize the magnetic flux shared by them and so the inductance. The performance of this new geometry has been compared with the conventional one, using Agilent HFSS field solver. After that, two multilevel inductors using this new geometry have been fabricated in a standard 0.6 μm three-metal CMOS process and measured     

A 0.1–20 GHz Low-Power Self-Biased Resistive-Feedback LNA in 90 nm Digital CMOS

In this letter, a 0.1–20 GHz low-power low noise amplifier (LNA) is presented. A novel self-biased resistive- feedback topology is proposed. Two inductors inside the feedback loop and a shunt-peaking inductor are exploited to extend the bandwidth. A PMOSFET with inductive degeneration is chosen as the load to boost the gain while maintaining low noise figure (NF) at high frequencies. A source-degeneration inductor is also introduced at the input transistor to ensure good input matching and stability over the entire bandwidth. All inductors are small due to the presence of feedback. The LNA was fabricated using a digital 90 nm CMOS process with 12.7 dB peak power gain, 3.3 dB minimum NF, and ${- 1}~{rm dBm}$ peak input-referred third-order intercept point (IIP3). With 12.6 mW power consumption and 0.12 ${rm mm}^{2}$ active area, this wideband LNA may replace distributed amplifiers (DAs) in many applications.      

Packaging-compatible high Q microinductors and microfilters forwireless applications

To meet requirements in mobile communication and microwave integrated circuits, miniaturization of the inductive components that many of these systems require is of key importance. At present, active circuitry is used which simulates inductor performance and which has high Q-factor and inductance; however, such circuitry has higher power consumption and higher potential for noise injection than passive inductive components. An alternate approach is to fabricate integrated inductors, in which lithographic techniques are used to pattern an inductor directly on a substrate or a chip. However, integrated inductors can suffer from low Q-factor and high parasitic effects due to substrate proximity. To expand the range of applicability of integrated microinductors at high frequency, their electrical characteristics, especially quality factor, should be improved. In this work, integrated spiral microinductors suspended (approximately 60 μm) above the substrate using surface micromachining techniques to reduce the undesirable effect of substrate proximity on the inductor performance are investigated. The fabricated inductors have inductances ranging from 15-40 nH and Q-factors ranging from 40-50 at frequencies of 0.9-2.5 GHz. Microfilters based on these inductors are also investigated by combining these inductors with integrated polymer filled composite capacitors     

衬底结构特征对硅基螺旋电感性能的影响

使用三维电磁场模拟的方法对不同硅衬底结构螺旋电感进行了模拟和分析.通过改变衬底的电导率、隔离层的厚度以及隔离层的材料、衬底引入硅锗合金层等模拟,分析了电感性能的变化.结果表明随着电导率的减小,电感的性能会增强,但改善的幅度会逐渐减小.厚的SiO2隔离层有利于减小衬底损耗,但是会给工艺增加难度.采用低k材料作为隔离层是改善电感性能的一种比较理想的方法.     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法 .这种方法是直接在硅衬底形成间隔的 pn结隔离以阻止螺旋电感诱导的涡流 .衬底 pn结间隔能用标准硅工艺实现而不需另外的工艺 .本文设计和制作了硅集成电路 ,测量了硅集成电感的 S参数并且从测量数据提取了电感的参数 .研究了衬底结隔离对硅集成电感的品质因素 Q的影响 .结果表明一定深度的衬底结隔离能够取得很好的效果 .在 3GHz,衬底 pn结隔离能使电感的品质因素 Q值提高4 0 % .     

MMIC用NiFe-SiO_x磁性金属颗粒膜电感研究

在蓝宝石基的氮化镓衬底上采用射频磁控溅射结合剥离的方法制作了NiFe-SiOx磁性金属颗粒膜,利用PECVD淀积绝缘层,制备出"SiN绝缘层/NiFe-SiOx薄膜/SiN绝缘层/金属线圈"结构的平面电感。测试表明,对于单圈电感,与无磁膜结构相对比在1 GHz时电感量有30%的提升,且对Q值影响不大;对于多圈电感,电感量与电感结构密切相关,当磁膜同时存在于线圈下和线圈之间时对电感量提升最大,但截止频率较低;而磁膜在电感线圈正下方的结构对电感量提升较前一种磁膜电感低,但截止频率较前一种磁膜电感高。     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法.这种方法是直接在硅衬底形成间隔的pn结隔离以阻止螺旋电感诱导的涡流.衬底pn结间隔能用标准硅工艺实现而不需另外的工艺.本文设计和制作了硅集成电路,测量了硅集成电感的S参数并且从测量数据提取了电感的参数.研究了衬底结隔离对硅集成电感的品质因素Q的影响.结果表明一定深度的衬底结隔离能够取得很好的效果.在3GHz,衬底pn结隔离能使电感的品质因素Q值提高40%.     

片上螺旋电感集总模型中衬底因子的分析与拟合

石英、高阻SOI、高阻硅等衬底上实现的电感具有比低电阻率衬底的电感更优的高频性能,因而研究基于不同衬底的电感性能,并在高频模型中进行精确的衬底因子表征就显得十分重要.综合考虑高频下的趋肤效应和邻近效应及衬底电磁损耗对电感性能的影响,实现了片上螺旋电感的集总元件模型,并通过与SOI、石英衬底的电感仿真参数及高阻硅衬底的电感测试参数进行了模型验证,结果表明,该模型拟合的S参数及Q值曲线能与仿真及测试结果吻合,同时模型中衬底因子的提取值与衬底性质相符合,因而该模型适用于片上电感的模拟与设计.     

MMIC用多层磁膜电感研究

采用磁控溅射生长磁膜工艺,结合BCB(苯并环丁烯)平坦化技术,首次制作了"金属线圈/磁膜/金属线圈(M/F/M)"和"磁膜/金属线圈/磁膜/金属线圈(F/M/F/M)"两种结构的多层磁膜电感,整个工艺与标准MMIC工艺兼容.在2 GHz处,"金属线圈/磁膜/金属线圈"结构电感的电感量为7.5 nH,品质因数为7.17,...     

13.56MHz RFID读写器天线的设计与仿真

为提高13.56 MHz RFID读写器天线的发射效率,并使其天线在实验室易于研发和试制,对13.56 MHz RFID天线系统的工作原理进行了简要介绍,在此基础上,把13.56 MHz RFID读写器天线线圈等效为PCB平面螺旋电感,利用HFSS软件建立模型并仿真得出电感值L、品质因子Q值等参数。其仿真结果得到的电感值与理论计算值相差0.03μH,在可接受的范围内。考虑到实际天线产生的寄生电容,提出了在天线末端加开路补偿线圈的方法,避免因寄生电容产生地电流而使天线线圈的磁场强度降低,仿真结果证实了该方法的可行性。     

陶瓷基板上的集成微电感模型与制作

对陶瓷基板上的集成微电感模型进行了分析.由于陶瓷基板的介电常数比Si基板低,电阻率极高,因此衬底损耗大大减小,从而有效提高了电感的Q值.同时,为了更好进行对比,研究中采用相同工艺在陶瓷基板和Si基板上同批制作了集成电感,两者的结构参数完全一致.测试结果表明,两者的电感值L基本相同,然而陶瓷基板上集成微电感Q值的峰值要比Si基板集成微电感高7左右,Si基板上Q值峰值在5 GHz以下,而陶瓷基板集成微电感的Q值峰值在10 GHz左右.     

Design issues for monolithic DC-DC converters

This paper presents various ideas for integrating different components of dc-dc converter on to a silicon chip. These converters are intended to process power levels up to 0.5W. Techniques for integrating capacitors and design issues for MOS transistors are discussed. The most complicated design issue involves inductors. Expressions for trace resistance and inductance estimation of on-chip planar spiral inductor on top metal layer of CMOS process are compared. These inductors have high series resistance due to low metal trace thickness, capacitive coupling with substrate and other metal traces, and eddy current loss. As an alternative, a CMOS compatible three-dimensional (3-D) surface micromachining technology known as plastic deformation magnetic assembly (PDMA) is used to fabricate high quality inductors with small footprints. Experimental results from a monolithic buck converter using this PDMA inductor are presented. A major conclusion of this work is that the 3-D "post-process" technology is more viable than traditional integrated circuit assembly methods for realizing of micro-power converters.     

Experimental analysis of the effect of metal thickness on the quality factor in integrated spiral inductors for RF ICs

The effect of metal thickness on the quality (Q-) factor of the integrated spiral inductor is investigated in this paper. The inductors with metal thicknesses of 5/spl sim/22.5 /spl mu/m were fabricated on the standard silicon substrate of 1/spl sim/30 /spl Omega//spl middot/cm in resistivity by using thick-metal surface micromachining technology. The fabricated inductors were measured at GHz ranges to extract their major parameters (Q-factor, inductance, and resistance). From the experimental analysis assisted by FEM simulation, we first reported that the metal thickness' effect on the Q-factor strongly depends on the innermost turn diameter of the spiral inductor, so that it is possible to improve Q-factors further by increasing the metal thickness beyond 10 /spl mu/m.