IEEE 802.11协议中GFSK调制解调的算法与实现

介绍了在IEEE802．11协议的跳频传输系统中，GFSK调制解调的实现原理。讨论了选择直接相位检测来实现解调的原因，并给出了一套低成本的实现方案。     

802.11 mesh网的安全研究

WMN（wireless Mesh Network）是一种动态的自组织、自配置的网络。网络中的各节点自动建立成一个Adhoc网络并保持一种网状连接。WMN具有前期投入低、系统容量大、维护简单、可靠性高等许多优点。802．11mesh网是一种802．11和mesh相结合的组网结构，它使用一组网状的无线路由器相连来提供一定区域的无线覆盖。由于802．11mesh网的一些特点，这种网络也带来了一些不同于传统802．11网络的一些新的安全挑战。     

数字GFSK调制解调的研究与实现

高斯频移键控（GFSK）是一种广泛应用于低数据速率的个人通信标准（如蓝牙）的调制方式。限于低功耗和低成本,GFSK收发机通常在模拟域设计。为了改进误比特率和提高不同的复杂设备之间的综合能力,数字GFSK解调技术应运而生。本文对数字GFSK调制解调算法进行研究与仿真,重点研究一种载波同步算法的实现。本文采用的这种载波同步方式是利用判决反馈差值补偿的方法来消除载波频率偏移。通过在MATLAB上进行仿真,在高斯白噪声环境中实现了理想误码率的GFSK传输仿真。     

基于自适应调制的OFDM系统

首先引入了一种可以在未来无线多媒体移动通信环境中提高数据传输速率和用户平均传输容量的系统，即基于自适应调制功能的正交频分复用（OFDM）系统的框图，然后分别利用无线LAN标准802．11a和IEEE 802．15．TG3a中规定参数对采用BPSK，QPSK，16QAM，64QAM四种调制方式的OFDM传输系统在瑞利衰减信道和存在多径效应的情况下进行了仿真，并对它们的BER性能进行了比较，最后对该系统作了客观分析。     

IEEE802.11g研究综述

IEEE802．11工作组近年来开始定义新的物理层标准IEEE802．11g。与以前的IEEE802．11协议标准相比，IEEE802．11g草案有以下两个特点：在2．4GHz频段使用正交频分复用(OFDM)调制技术，使数据传输速率提高到20Mbit／s以上；能够与IEEE     

OFDM与高速无线局域网

描述了已被IEEE802．11，ETIS，MMAC采用和发展了的一种基于OFDM调制方法的无线局域网标准，给出了一般实现的框图，还在最后讨论了OFDM调制方式和SDMA多址方式相结合在WLAN中的应用和实际意义。     

无线局域网标准IEEE802．11g的技术优势

无线局域网标准IEEE802．11g与其它IEEE802．11系列标准相比具有明显的技术优势。在2．4G频段使用正交频分复用(OFDM)调制技术，使数据传输速率提高到20Mbps以上；同时能够与应用广泛的802．11b共存在同一AP的网络里，保障了后向兼容性。本文着重介绍IEEE802．11g的技术优势。     

数字GFSK调制解调的算法与实现

高斯频移键控（Gauss frequencyShift Keying,GFSK）是一种广泛应用于低数据速率的个人通信标准（如蓝牙）的调制方式。限于低功耗和低成本,GFSK收发机通常在模拟域设计。为了改进误比特率和提高不同的复杂设备之间的综合能力,数字GFSK调制解调技术应运而生。在该文,将着重讨论最小平方（LS）与最大似然估计法（MS）是利用计算机辅助技术来实现GFSK载波恢复。通过估测误差方差的分析,我们发现LS/ML载波频率偏移估计法优于传统DFT法。除此之外,本方法也能有效地处理直流的数据源。通过在MATLAB上进行仿真,在高斯白噪声环境中实现了理想误码率的GFSK传输仿真。     

WLAN 802.11b中的调制技术--CCK

介绍无线局域网IEEE802．11标准中物理层采用的调制技术——CCK(补码键控)，详细介绍了CCK的基本原理和系统框图，并分析它们的性能。     

802.1 I p Physical Layer the OFDM Baseband Modulator FPGA Implementation

基于IEEE802．11p标准的车辆无线通信系统作为智能交通系统的一部分,能极大地改善交通系统的安全性、有效性和实时性。该文详细描述了作者对车辆无线通讯系统关键技术进行的相关研究内容,并且在cyclnneⅢEP3C120F平台上实现了一种基于IEEE802．11p标准的物理层OFDM基带调制系统,效果理想,有很好的移植性。     

基于DSP和RF ASIC芯片的GFSK调制解调器

介绍了一种基于DSP和RFASIC芯片的GFSK正交调制解调器的设计和研制方案。回顾了传统的GFSK调制器的硬件实现方法,分析了GFSK正交调制器的基带构成,讨论了在SYSTEMVIEW平台下GFSK调制解调器的系统仿真,并将仿真算法用于TI VC5402 DSP,在子系统级RFASIC芯片U2793B和AD6459的硬件环境中,较好地实现了GFSK正交调制解调功能。     

New method of analyzing BER performance of GFSK with postdetectionfiltering

This paper describes the theoretical performance of a frequency-hopping system using Gaussian-filtered FSK (GFSK), which is a promising candidate for 2.4-GHz wireless local area networks (WLAN). We have improved previous methods to calculate the bit-error rate (BER) performance of the GFSK system by considering the effect of a postdetection filter in the first-order approximation. The improved method is applicable when the single-sided bandwidth of the postdetection filter is wider than the bandwidth containing 99% of the GFSK signal energy. It is used to calculate the BER performance as well as the dependence of the BER on the level of interchannel interference. The calculated performance of the GFSK system suggests that the postdetection filter is very effective in reducing interchannel interference. The feasibility of a GFSK system with a 1-Mbd symbol rate and 0.32 modulation index is confirmed by the combination of a predetection filter with a 0.85-MHz bandwidth and a postdetection filter with a 0.8-MHz single-sided bandwidth     

无线局域网关键技术与发展综述

基于IEEE802.11标准全面介绍了无线局域网，包括其概念、发展历史、特点、构件及体系结构、发展前景，详细讲述了IEEE802.11协议的帧格式以及实现IEEE802.11WLAN所需的几项关键技术。     

A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibratedΣ-Δ frequency synthesizer

This paper describes a new sigma-delta (Σ-Δ) frequency synthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK) modulation. The key innovation is an automatic calibration circuit which tunes the phase-locked loop (PLL) response to compensate for process tolerance and temperature variation. The availability of this new calibration method allows the use of precompensation techniques to achieve high data rate modulation without requiring factory calibration. The calibration method can be applied to GFSK/GMSK modulation and also M-ary FSK modulation. The PLL, including 1.8-GHz voltage controlled oscillator (VCO), Σ-Δ modulator, and automatic calibration circuit, has been implemented in a 0.6-μm BiCMOS integrated circuit. The test chip achieves 2.5 Mb/s using GFSK and 5.0 Mb/s using 4-FSK     

Fractional Multi‐bit Differential Detection Technique for Continuous Phase Modulation

A new low‐complexity differential detection technique, fractional multi‐bit differential detection (FMDD), is proposed in order to improve the performance of continuous phase modulation (CPM) signals such as Gaussian minimum shift keying (GMSK) and Gaussian frequency shift keying (GFSK). In comparison to conventional one‐bit differential detected (1DD) GFSK, the FMDD‐employed GFSK provides a signal‐to‐noise ratio advantage of up to 1.8 dB in an AWGN channel. Thus, the bit‐error rate performance of the proposed FMDD is brought close to that of an ideal coherent detection while avoiding the implementation complexity associated with the carrier recovery. In the adjacent channel interference environment, FMDD achieves an even larger SNR advantage compared to 1DD.     

Efficient encoding of IEEE 802.11n LDPC codes

Addressed is the issue of LDPC coding for the emerging IEEE 802.11n standard. An efficient encoding algorithm is proposed. The algorithm is simple and easy to implement. The memory requirement is trivial     

Quality of service support in IEEE 802.11 wireless ad hoc networks

Supporting Quality of Service (QoS) in wireless networks is a challenging problem. The IEEE 802.11 LAN standard was developed primarily for elastic data applications. In order to support the transmission of real-time data, a polling-based scheme called the point coordination function (PCF) was introduced in IEEE 802.11. However, PCF was not able to meet the desired and practical service differentiation requirements to fulfill the need of real-time data. Therefore, Task Group E of the IEEE 802.11 working group released several IEEE 802.11e drafts, whose main task is to support QoS in IEEE 802.11 LANs. The polling scheme of PCF is extended in IEEE 802.11e into the more complex hybrid coordination function (HCF). We found that HCF has several performance issues that may affect its anticipated performance. In this paper, we address these issues and propose a QoS enhancement over PCF, called enhanced PCF (EPCF) that enables Wireless LAN to send a combination of voice, data and isochronous data packets using the current IEEE 802.11 PCF. First, we compare the performance of the proposed model (EPCF) with the HCF function of the IEEE 802.11e through simulation. Second, we extend the proposed model (EPCF) to work in a multihop wireless ad hoc mode and present the advantages and limitations in this case. Simulation results demonstrate an enhanced performance of our scheme over the legacy PCF and a comparable performance to the IEEE 802.11e HCF in terms of the average delay and system throughput. However, EPCF is much simpler than HCF, provides flow differentiation, and is easy to implement in the current IEEE 802.11 standard.     

A 0.18-$muhbox{m}$ CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning

A fully integrated 2-MHz Gaussian frequency-shift keying (GFSK) analog front end for low-IF receivers is presented. The analog GFSK demodulation uses a Bessel-based quadrature discriminator and a differentiator-based data decision circuit, eliminating the need for analog–digital converters while enabling high sensitivity and large frequency offset tolerance. The analog front end consists of a fifth-order Butterworth low-pass prefilter, a seven-stage limiter, a quadrature discriminator with a fourth-order Bessel phase-shift network, a fourth-order Butterworth low-pass postfilter, and a differentiator-based data decision circuit. The prefilter, Bessel phase shifter, postfilter, and differentiator are built using identical $Gm{-}C$ cells and tuned across process variations with a single master–slave phase-locked loop. The GFSK analog front end is implemented in a 1.8-V 0.18-${rm mu}hbox{m}$ CMOS process, recovering 1-Mb/s input data from a 2-MHz GFSK signal with maximum frequency deviation of $pm$160-kHz, frequency offset tolerance from $-$ 38% to $+$ 47%, and input sensitivity of $-$53 dBm and consuming 7 mA of current.