Board-level reliability of Pb-free solder joints of TSOP and various CSPs

To evaluate various Pb-free solder systems for leaded package, thin small outline packages (TSOPs) and chip scale packages (CSPs) including leadframe CSP (LFCSP), fine pitch BGA (FBGA), and wafer level CSP (WLCSP) were characterized in terms of board level and mechanical solder joint reliability. For board level solder joint reliability test of TSOPs, daisy chain samples having pure-Sn were prepared and placed on daisy chain printed circuit board (PCB) with Pb-free solder pastes. For CSPs, the same composition of Pb-free solder balls and solder pastes were used for assembly of daisy chain PCB. The samples were subjected to temperature cycle (T/C) tests (-65/spl deg/C/spl sim/150/spl deg/C, -55/spl deg/C/spl sim/125/spl deg/C, 2 cycles/h). Solder joint lifetime was electrically monitored by resistance measurement and the metallurgical characteristics of solder joint were analyzed by microstructural observation on a cross-section sample. In addition, mechanical tests including shock test, variable frequency vibration test, and four point twisting test were carried out with daisy chain packages too. In order to compare the effect of Pb-free solders with those of Sn-Pb solder, Sn-Pb solder balls and solder paste were included. According to this paper, most Pb-free solder systems were compatible with the conventional Sn-Pb solder with respect to board level and mechanical solder joint reliability. For application of Pb-free solder to WLCSP, Cu diffusion barrier layer is required to block the excessive Cu diffusion, which induced Cu trace failure.     

WLCSP封装技术中的集成无源器件

芯片规模封装技术一直倍受高性能、小形状因素解决方案在各类应用中的关注。芯片规模封装与球栅阵列(BGA)封装之间的区别变得不可分辨,已成为“细间距BGA”的同义词。芯片规模封装成本也是业界关注的焦点之一。芯片规模晶圆级封装是提供小形状、高性能和低成本的最快途径。论述了集成无源器件加工、低成本化的晶圆级芯片规模封装技术。     

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

This paper describes three circuit techniques for a DDR1/DDR2-compatible chip architecture designed for both high-speed and high-density DRAMs: 1) a dual-clock input-latch scheme, which reduces the excessive timing margin for random input commands by using a pair of latch circuits controlled by dual-phase one-shot clock signals, achieves a 0.9-ns reduction in cycle time from 3.05 to 2.15 ns; 2) a hybrid multi-oxide output buffer reduces the area penalty of the output buffer caused by compatible chip design from 1.35% to 0.3%; and 3) a quasi-shielded distributed data transfer scheme enables a 2.6-ns reduction in access time to 10.25 ns in both 2-b and 4-b prefetch operations. By using these techniques, we developed a 175.3-mm/sup 2/ 1-Gb SDRAM that operates as an 800-Mb/s/pin DDR2 or 400-Mb/s/pin DDR1.     

Advanced Packaging: The Redistributed Chip Package

The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current wirebond ball grid array (BGA) and flip chip BGA packaging. Devices are encapsulated into panels while routing of signals, power, and ground is built directly on the panel. The RCP panel and signal build up lowers the cost of the package by eliminating wafer bumping and substrates thereby enabling large scale assembly in panel form. The build up provides better routing capabilities and better integration. Also, by eliminating bumping, the device interconnect is inherently Pb-free, and the stress of the package is reduced enabling ultra-low-k device compatibility. The panel is created by attaching the device active side down to a substrate, encapsulating and curing the devices, grinding to desired thickness, and then removing the substrate. Signal, power, and ground planes are created using redistribution-like processing. Multilayer metal RCP packages have passed 40 to 125 C air-to-air thermal cycling and HAST after MSL3/260 preconditioning.     

基于ANSYS 的DDR4 SDRAM 信号完整性仿真方法研究

半导体技术快速发展,双倍数据速率同步动态随机存取存储器(Double Data Rata Synchronous Dynamic Random Access Memory, DDR SDRAM)的信号完整性问题已成为设计难点。文中提出了一种基于ANSYS 软 件和IBIS 5. 0 模型的DDR4 SDRAM 信号完整性仿真方法。利用IBIS 5. 0 模型中增加的复合电流(Composite Current) 、同步开关输出电流等数据,对DDR4 SDRAM 高速电路板的信号完整性进行更准确的仿真分析。仿真结果 表明:高速信号在经过印制板走线和器件封装后,信号摆幅和眼图都有明显恶化;在仿真电路的电源上增加去耦 电容后,信号抖动和收发端同步开关噪声(Synchronous Switching Noise, SSN)都得到明显改善;在不加去耦电容的 情况下,将输入信号由PRBS 码换成DBI 信号,接收端的同步开关噪声有所改善,器件功耗可以降为原来的一半。     

BGA器件及其常见的形式

BGA器件不仅能够满足现在已有的其它组件所不能够提供的高性能、大量I/O数量的应用要求,也给如今的有引脚元器件提供了一种可靠的可替换方案。对于在组件体的底部位置安置有大量焊球阵列的BGA器件来说有四种主要的类型。表面阵列配置的组装技术将会成为电子组装业最主要的发展潮流。     

Electrical evaluation of flip-chip package alternatives for nextgeneration microprocessors

Two styles of flip-chip packages for next-generation microprocessors were designed: a low-cost organic ball-grid-array (BGA) and a thin-film-on-ceramic land-grid array (LGA). Simultaneous switching output (SSO) noise, and core noise were measured. Although SSO was improved by a factor of two over the previous generation of packaging, core noise was still quite significant. We found that core noise is best managed by placing low-inductance capacitance close to the noise source, i.e., using on-chip capacitors, coupled planes in the package, or on-package bypass capacitors. Because of the lower impedance of its power planes, the ceramic package showed significantly better electrical performance than the organic. Addition of on-package bypass capacitors greatly narrows the gap between the two packages     

RF flip-module BGA package

We recently described a flip-chip package with integrated thin-film inductors and capacitors in a VCO tank circuit of a single chip GSM transceiver integrated circuit (IC). By embedding the passive components in a Si-on-Si substrate, we eliminated spurious resonances that were caused by the parasitics of the original 64-TQFP IC package. However, compared with the bare die, the resultant Si-on-Si structure is larger in all dimensions due to the inclusion of a flip-chip mounted transceiver IC and a surface-mount varactor. We have developed a novel BGA package structure with a hole milled in the center to accommodate the silicon-on-silicon assembly. The interconnections rely exclusively on flip-chip solder technology. To verify that the package does not degrade the performance of the RF circuits, we have performed electromagnetic field simulations to extract critical inductance and capacitance parameters. Parasitic inductances of the original TQFP and the new packages are comparable due to their similar dimensions. None the less, a major advantage of the new package structure is that it permits the integration of key passive components inside the package where they are unaffected by package parasitic impedances     

A 10 Gb/s hybrid-integrated receiver array module using a planarlightwave circuit (PLC) platform including a novel assembly regionstructure

A planar lightwave circuit (PLC) platform for optoelectronic hybrid integration shows potential for achieving 10 Gb/s operation. It uses AuSn bump-type bonding pads on a silica layer to decrease parasitic capacitance, which limited the CR time constant in the optical chip assembly region, and two-layer electrical wiring to reduce parasitic inductance, which caused resonance in the electrical circuit region. An arrayed receiver module fabricated by integrating a two-channel monolithic opto-electronic integrated circuit (OEIC) chip on the PLC platform demonstrated a 3 dB-bandwidth of 8 GHz in both channels, which is equal to the bandwidth of the OEIC chip. This shows the feasibility of using this PLC platform for multichannel 10 Gb/s operation. Furthermore, this PLC platform can combine the versatile optical circuit functions of a PLC, such as an arrayed-waveguide grating wavelength multiplexer, with the high-speed signal processing function of mature electronic IC circuits. Consequently, this platform is a key device that will lead to high-capacity optical signal processing systems using optical wavelength/frequency routing     

SMT-compatible large-tolerance "OptoBump" interface for interchip optical interconnections

A new optical interface called OptoBump has been developed to couple optoelectronic packages to an optoelectronic printed circuit board, thus enabling economical chip-to-chip optical interconnections. The optoelectronic packages have vertical-cavity surface-emitting laser (VCSEL) and PD-array chips in their cavity and an large scale integrated (LSI) mounted on top. A package converts high-speed electrical signals from the LSI into an array of optical signals, which are emitted from the bottom. The PCB contains integrated polymer optical waveguides to optically connect packages, and the use of surface-mount technology (SMT) to mount packages on the printed circuit board (PCB) keeps assembly costs low. The key to making the OptoBump interface fully compatible with SMT is the integration of microlens arrays directly into both packages and the PCB. A wide, collimated optical beam couples a package to the board across a narrow air gap and provides a large tolerance to misalignment during the SMT process. This paper explains the concept of the OptoBump interface, the optical coupling design by ray-trace simulation, and the fabrication of polymer microlenses and polymer waveguides. Experimental results revealed that the OptoBump interface provides a large tolerance of /spl plusmn/50 /spl mu/m, which is large enough for use with SMT. The OptoBump interface can replace high-speed electrical wiring at the chip level and also offers the benefit of not having any optical fibers or connectors on the board. Thus, it has the potential to bring about a revolutionary change in optoelectronic packaging.     

视频格式转换系统中DDR控制器设计

提出了面向高清的视频格式转换系统,设计了一种基于状态机且适用于视频格式转换的DDR SDRAM控制器系统结构和状态转移控制流程.该控制器能实现2片DDR SDRAM乒乓读写切换,完成整个视频的传输.最后对控制器的电路进行了仿真,并在Xilinx的Spartan3E系列上实现了DDR SDRAM的连续读写,为集成电路技术...     

Modeling the power and ground effects of BGA packages

Ground bounce noise and power supply noise are the major concerns in the electrical design of ball grid array (BGA) packages, therefore accurate models of the package's ground and power structures are needed for circuit simulators. This innovative new software is targeted for the engineer who, at his laptop PC, can rapidly generate accurate power and ground electrical models of an entire BGA package. Using the accepted approximation equations of Grover and Walker [1973 and 1990], the program was designed to be fast and portable contrasting other methods of modeling in which such attributes were sacrificed for greater accuracy. Operation consists of entering the available data, and in just minutes retrieving a parameter listing and two sub-circuit models simultaneously, one circuit for power and one for the ground of the package. The values of inductance and capacitance generated by the program closely match those generated by Grover, Walker, and Caggiano [1995, 1997]. The listing can be used as an evaluation tool for a specific package (e.g., during a design review when critical information is needed quickly) while the circuit models can be used in a simulation program with integrated circuit emphasis (SPICE) circuit simulation of the integrated circuit (IC). These separate models, designed with as few components as possible in order to reduce the complexity of the SPICE topology while still maintaining accuracy, can be either incorporated with signal package models or can be simulated alone     

400-MHz random column operating SDRAM techniques with self-skewcompensation

High-speed data transfer is a key factor in future main memory systems. DDR SDRAM (double-data-rate synchronous-DRAM) is one of the candidates for high-speed memory. In this paper we present three techniques to achieve a short access time and high data transfer rate for DDR-SDRAM's. First, a self-skew compensating technique enables 400-Mbit/s address and data detection. Second, a novel trihierarchical WL scheme realizes multibank operation without access or area penalties. Third, an interleaved array access path doubles the array operating frequency and it enables 400-MHz random column operation. A 16-bank 256-Mbit DDR SDRAM circuit has been designed, and the possibility of the realization of random column 200 MHz×32 DDR operation, namely, 1.6-Gbyte/s data rate operation, has been confirmed     

The Effects of Package Parasitics on the Stability of Microwave Negative Resistance Devices

The results of investigations of the effect of parasitic package elements on the behavior of negative resistance amplifiers are presented. Three different package styles were considered. Also two different lead configurations were used. The packages were all mounted in 7-mm coaxial transmission line. The impedance of packages with and without leads was measured from 4 to 18 GHz using a manual network analyzer. These data were used as the basis for calculations to determine the values of elements in a simple three-element equivalent circuit model of the package. Using the equivalent circuit model experimentally derived for each package style, the impedance seen by the chip through the package to a 50-/spl Omega/ load was calculated. Broad-band curves of the impedance seen by the chip are presented. The experimentally derived model of the package permits matching of chip and package for stability.     

Encapsulation process development for flexible-circuit based chip scale packages

The ultimate driving forces for the development of small form-factor chip scale packages (CSPs) are the market demands for small, light and high performance products. The flex-based /spl mu/BGA technology has been a very successful package format, and tremendous efforts have been implemented in the process development for the technology. In this article, three flex-based chip scale packages (based on patented /spl mu/BGA technology) will be discussed. The focus will be on the encapsulation process development. Because of the unique package structures and material sets used in the flex-based CSPs, various encapsulation challenges were raised. The encapsulation solutions are compared and discussed for each type of flex-based /spl mu/BGA technologies, including the dispensing pump technologies, material characterization, process characterization and optimization. Based on the evaluation results, type C /spl mu/BGA technology is recommended for its simple assemble process flow, balanced protection on beam leads and solder ball joints and shorter manufacturing cycle time as well.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.     

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchicalsquare-shaped memory block and distributed bank architecture

This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 μm² cell and 581.8 mm² small die area are achieved using 0.15-μm CMOS technology. The ×61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described     

0.5mm间距BGA芯片的PCB设计

目前,在高速PCB设计中,0.8mm间距BGA芯片的应用已非常普遍,但0.5mm间距BGA芯片的设计和焊接应用则相对较少。文章结合多层线路板的叠层规则、布线设计、信号回流以及钻孔工艺等技术,采用在0.5mm间距BGA芯片的焊盘上直接设计盘中通孔和一阶盲孔。在将PCB成本控制在规定预算范围内的同时,成功的将0.5mm间距BGA芯片应用在高密度互连PCB的研究与开发中。从生产出小批量单板的焊接情况看,系统上电后运行稳定,不存在短路和虚焊情况,从而较好的实现了电路工作性能,达到预先设计目标。     

Qualification approaches and thermal cycle test results for CSP/BGA/FCBGA

Qualification of newly developed multifunctional electronic packages, e.g. system in a package (SIP), are becoming complex at the package level and even more at the assembly and system levels. After many years of data collection, just recently industry agreed to release an industry-wide specification for single die area array package assembly qualification.Probability risk assessment, being implemented by NASA for space flight missions, may be narrowed at the element level for advanced electronic systems and SIP, and further narrowed at the electronic subsystem level. This paper will review the key elements of an industry-wide specification recently published by the IPC (association connecting electronics industries). It will report on a few other unique qualification approaches that are currently being either implemented or developed for risk reduction in high reliability applications. Risk level assessment based 2-P, 3-P, and LogNormal distributions will be compared for plastic ball grid array (PBGA) and flip chip BGA (FCBGA). For this case, risks are compared using cycles-to-failures (CTFs) test results for temperature ranges of −30 to 100 °C and 0 to 100 °C (two profiles).In addition, CTFs up to 1,500 cycles in the range of −55 to 125 °C for a 784 I/O FCBGA (flip chip BGA, a 175 I/O FPBGA (fine pitch BGA)), and a 313 I/O PBGA (plastic BGA) are compared. Inspection results along with scanning electron microscopy and optical cross-sectional photos revealing damage and failure mechanisms are also included.