A miniaturized bulk micromachined triaxial accelerometer fabricated using deep reactive etching through a multilevel thickness membrane

We present the design, fabrication and characterization of an application specific triaxial accelerometer for post-surgery heart monitoring. The accelerometer chip is designed as a 2?×?4?×?1.2?mm³ chip with nominal acceleration range of?±4?g and frequencies below 50?Hz. It has been fabricated using a multiproject wafer service with an additional deep reactive ion etching process to obtain controlled etch-through of membranes of 3, 23 and 400?μm thicknesses simultaneously. The novelty of the work presented here is the bulk micromachining technique using both deep reactive dry etching and alkali-based anisotropic wet etching of single crystal (100) silicon wafers used to obtain a space efficient design. Proof of concept is demonstrated with preliminary testing, with an acceleration sensitivity of?~0.04 mv/V/g for out of plane (z axis) acceleration.     

Micromachining of buried micro channels in silicon

A new method for the fabrication of micro structures for fluidic applications, such as channels, cavities, and connector holes in the bulk of silicon wafers, called buried channel technology (BCT), is presented in this paper. The micro structures are constructed by trench etching, coating of the sidewalls of the trench, removal of the coating at the bottom of the trench, and etching into the bulk of the silicon substrate. The structures can be sealed by deposition of a suitable layer that closes the trench. BCT is a process that can be used to fabricate complete micro channels in a single wafer with only one lithographic mask and processing on one side of the wafer, without the need for assembly and bonding. The process leaves a substrate surface with little topography, which easily allows further processing, such as the integration of electronic circuits or solid-state sensors. The essential features of the technology, as well as design rules and feasible process schemes, will be demonstrated on examples from the field of μ-fluidics     

Hole-type two-dimensional photonic crystal fabricated in silicon on insulator wafers

We report the realization of two-dimensional (2D) photonic crystal (PhC) holes array using synthesized processing techniques of deep UV lithography, time-multiplexed reactive ion etching (TMRIE) and focus ion beam (FIB) etching. In this study, mixed density of holes and waveguide patterns of 2D PhC structures was first formed in silicon on insulator wafers through use of a scanner. Ultra wide grooves were then defined, aligned to the deep submicron size devices. Following deep etching of more than 50 μm by TMRIE, PhC structures were then revealed for device etching. Such design of fabrication process allows realization of disparate pattern dimensions and also etching depths. Through avoidance of etch lag effect, notching of devices at interface of device silicon and buried oxide layer was avoided. At the same time, through a singular FIB etch in the final step of the process following buried oxide release for PhC structures on critical dimension structures, severe loading effects of such structures were avoided to enable a wide process window of lithography and etch.     

Alternative technology used to manufacture semitransparent monocrystalline silicon solar cells

This paper presents the manufacturing technology of a new semitransparent solar cell that can be used for building integrated applications. Diluted tetramethylammonium hydroxide and isopropyl alcohol mixture is used to create uniform and reproducible pyramidal textures on the silicon wafers, thus reducing surface reflectance. Arbitrary pattern of holes can be etched using 5 wt % tetramethylammonium hydroxide solution. Ammonium persulfate powder has to be dissolved in the bulk etchant in order to maintain a stable 1.34 μm/min etching rate over the 3.5 h etching process. The ARC layer is the 90 nm thick silicon dioxide remaining after the anisotropic etching. The efficiency of the semitransparent solar cell is 6.12 % including grid contact and silicon through-hole areas, the transparency reached is 6.7 %, weighted surface reflectance is 4.31 %.     

A dielectrophoretic chip packaged at wafer level

The paper presents a dielectrophoretic chip, fully enclosed, with bulk silicon electrodes fabricated using wafer-to-wafer bonding techniques and packaged at the wafer level. The silicon electrodes, which are bonded to two glass dies, define in the same time the walls of the microfluidic channel. The device is fabricated from a silicon wafer that is bonded (at wafer level) anodically and using SU8 photoresist between two glass wafers. The first glass die includes drilled holes for inlet/outlet connections while the second glass die assure the electrical connections, through via holes and a metallization layer, between the silicon electrodes and a printing circuit board.     

A dielectrophoretic chip packaged at wafer level

The paper presents a dielectrophoretic chip, fully enclosed, with bulk silicon electrodes fabricated using wafer-to-wafer bonding techniques and packaged at the wafer level. The silicon electrodes, which are bonded to two glass dies, define in the same time the walls of the microfluidic channel. The device is fabricated from a silicon wafer that is bonded (at wafer level) anodically and using SU8 photoresist between two glass wafers. The first glass die includes drilled holes for inlet/outlet connections while the second glass die assure the electrical connections, through via holes and a metallization layer, between the silicon electrodes and a printing circuit board.

     

A MEMS guide plate for a high temperature testing of a wafer level packaged die wafer

This paper describes the design and fabrication of a MEMS guide plate, which was used for a vertical probe card to test a wafer level packaged die wafer. The size of the fabricated MEMS guide plate was 10.6 × 10.6 cm. The MEMS guide plate consisted of 8,192 holes to insert pogo pins, and four holes for bolting between the guide plate and the housing. To insert pogo pins easily, an inclined plane was defined at the back of each hole. Pitch and diameter of the hole were 650 and 260 μm, respectively. In order to define inserting holes and inclined planes at an exact position, silicon MEMS technology was used such as anisotropic etching, deep reactive etching and more. Silicon was used as the material of the guide plate to reduce alignment mismatch between the pogo pins and solder bumps during a high temperature testing. A combined probe card with the fabricated MEMS guide plate showed good x–y alignment and planarity errors within ±9 and ±10 μm at room temperature, respectively. In addition, x–y alignment and planarity are ±20 and ±16 μm at 125°C, respectively. The proposed MEMS guide plate can be applied to a vertical probe card for burn-in testing of a wafer level packaged die wafer because the thermal expansion coefficient of the MEMS guide plate and die wafer is same.     

Membrane microcantilever arrays fabrication with PZT thin films for nanorange movement

Lead zirconate titanate (PZT) piezoelectric thin films have been prepared by sol-gel method to fabricate microcantilever arrays for nano-actuation with potential applications in the hard disk drives. In order to solve the silicon over-etching problem, which leads to a low production yield in the microcantilever fabrication process, a new fabrication process using DRIE etching of silicon from the front side of the silicon wafer has been developed. Silicon free membrane microcantilevers with PZT thin films of 1 μm in thickness have been successfully fabricated with almost 100% yield by this new process. Annealing temperature and time are critical to the preparation of the sol-gel PZT thin film. The fabrication process of microcantilever arrays in planar structure will be presented. Key issues on the fabrication of the cantilever are the compatible etching process of PZT thin film and the compensation of thin film stress in all layers to obtain a flat multi-layer structure.     

基于金硅原电池保护电容加速度计的制作

提出并实现了一种利用SoI结合金硅原电池保护和反熔丝制作电容式加速度计的新工艺方法。该工艺用SoI顶层硅制作梁和上电极,用衬底制作质量块。采用DRIE从正面刻蚀形成释放孔,TMAH腐蚀实现质量块的释放,在TMAH腐蚀过程中利用金硅原电池保护实现梁和表面极板的保护。在TMAH腐蚀完成前,反镕丝保持断开状态,腐蚀完成后,击穿反镕丝形成导通状态。通过测量金和硅的极化曲线得到60℃25%TMAH中实现原电池保护的金硅面积比不小于5∶1。成功制作成电容式加速度计结构,释放前后梁宽度均在9.4～10μm范围内,表明原电池保护有效。击穿后反熔丝并联导通电阻为5～25 kΩ之间。     

A MEMS sandwich differential capacitive silicon-on-insulator accelerometer

A differential capacitive accelerometer with simple process is designed, simulated, and fabricated. To achieve a precision structure dimension with fewer processing steps, the silicon device layer transfer technology is being used to built a sandwich accelerometer based on a silicon-on-insulator (SOI) wafer, which was assembled by glass-si-glass multilayer anodic bonding. Deep reactive ion etching is being used to define symmetric beams and large mass block of equal thickness together in SOI device layer (up to 100 μm) in a single step to avoid alignment error in double side process. An actual accelerometer which is designed for 50 g measure range is fabricated with six lithography steps. Measurement results show 0.1166 V/g sensitivity and 0.022 % nonlinearity error in ±1 g gravity static response test. The accelerometer also provides a power spectrum less than 10.49 μVrms/Hz^1/2 (89.97 μg/Hz^1/2) in a non-isolated laboratory environment with a capacitive interface circuit.     

Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

In this paper a novel process to bond and, at the same time, to electrically connect a silicon wafer to a glass wafer is presented. It consists of a low temperature anodic bonding process between silicon and glass by using a glass wafer with etched channels in order to contain metal tracks. The glass-to-silicon anodic bonding process at low temperatures (not exceeding 300°C) assures a strong mechanical link (Berthold et al. in Transducers 1999, June:7–10, 1999). The electrical contacts between the metal pads on the backside of a silicon wafer and the metal pads on the glass wafer are achieved by sintering and diffusion of metals due to a kind of thermo compression bonding. This bonding method permits a high vertical control due to a well-controlled etching of the cavity depth and to the thickness precision of both metallization (pads on silicon wafers and metal tracks on glass wafer). This IC-processing compatible approach opens up the way to a new electrical connection concept keeping, at the same time, a strong mechanical bond between glass and silicon wafers for an easier fabrication of a more complex micro-system.     

Comparison of etch characteristics of KOH,TMAH and EDP for bulk micromachining of silicon (110)

Bulk micromachining in Si (110) wafer is an essential process for fabricating vertical microstructures by wet chemical etching. We compared the anisotropic etching properties of potassium hydroxide (KOH), tetra-methyl ammonium hydroxide (TMAH) and ethylene di-amine pyro-catechol (EDP) solutions. A series of etching experiments have been carried out using different etchant concentration and temperatures. Etching at elevated temperatures was found to improve the surface quality as well as shorten the etching time in all the etchants. At 120°C, we get a smooth surface (Ra = 21.2 nm) with an etching rate 12.2 μm/min in 40wt% KOH solution. At 125°C, EDP solution (88wt%) was found to produce smoothest surface (Ra = 9.4 nm) with an etch rate of 1.8 μm/min. In TMAH solution (25wt%), the best surface roughness was found to be 35.6 nm (Ra) at 90°C with an etch rate of 1.18 μm/min. The activation energy and pre-exponential factor in Arrhenius relation are also estimated from the corresponding etch rate data.

     

Glass Blowing on a Wafer Level

A fabrication process for the simultaneous shaping of arrays of glass shells on a wafer level is introduced in this paper. The process is based on etching cavities in silicon, followed by anodic bonding of a thin glass wafer to the etched silicon wafer. The bonded wafers are then heated inside a furnace at a temperature above the softening point of the glass, and due to the expansion of the trapped gas in the silicon cavities the glass is blown into three-dimensional spherical shells. An analytical model which can be used to predict the shape of the glass shells is described and demonstrated to match the experimental data. The ability to blow glass on a wafer level may enable novel capabilities including mass-production of microscopic spherical gas confinement chambers, microlenses, and complex microfluidic networks     

Micromachined flat-walled valveless diffuser pumps

The first valveless diffuser pump fabricated using the latest technology in deep reactive ion etching (DRIE) is presented. The pump was fabricated in a two-mask micromachining process in a silicon wafer polished on both sides, anodically bonded to a glass wafer. Pump chambers and diffuser elements were etched in the silicon wafer using DRIE, while inlet and outlet holes are etched using an anisotropic etch. The DRIE etch resulted in rectangular diffuser cross sections. Results are presented on pumps with different diffuser dimensions in terms of diffuser neck width, length, and angle. The maximum pump pressure is 7.6 m H₂O (74 kPa), and the maximum pump flow is 2.3 ml/min for water     

A low-cost through via interconnection for ISM WLP

Wafer level packaging (WLP) for image sensor device has the advantage of small size, high performance and low cost. In WLP technology, in order to form electrical interconnection from image sensor contact pad to the backside of the wafer, several structures have been developed, such as T-contact and through silicon via (TSV). In this paper, a wafer level package of image sensor with new type TSV electrical interconnection for image sensor pad is presented. The target of this development is to reduce process cost and difficulty, and increase yield of image sensor packaging. Key fabrication processes includes glass protecting wafer bonding, device wafer thinning, backside through via etching, via passivation layer deposition, pad oxide opening, via filling and backside re-routing layer formation, etc. Compared to large opening area of tapered via on the backside of CMOS image sensor wafer, only small opening area is need for making via interconnection with vertical sidewall presented in this paper. A fillet structure at bottom corner of via holes can help to reduce sequent process difficulty, so that low-cost and simplified unit processes are successfully adopted in the fabrication process for through via formation. The through via interconnection shows good electrical connection performance, and high-quality photo images are obtained by packaged image sensor device.     

Ultra thin ICs and MEMS elements: techniques for wafer thinning,stress-free separation,assembly and interconnection

 Ultra thin chips with a thickness below 30 μm offer low system height, low topography and show enhanced mechanical flexibility. These properties enable diverse use possibilities and new applications. However, advanced wafer thinning, adapted assembly and interconnection methods are required for this technology. A new process scheme is proposed that allows manufacturing of ultra thin fully processed wafers. Secure handling is achieved by means of carrier substrates using reversible adhesive tapes for connection of support and device wafers. Well established backgrinding and etching techniques are used for wafer thinning. To avoid mechanical damage of thin ICs the “Dicing-by-Thinning” (DbyT) concept is introduced to process flow. Best results are obtained when preparing dry etched chip grooves at front side of device wafer and opening these trenches during backside thinning. The new process scheme was also applied to wafers with highly topographic surfaces. Results of 40 μm thin wafers with 15 μm high Nickel bumps are presented. Three different assembly methods are described, interconnection through the thin chip, face down assembly and isoplanar contacting. Received: 6 July 2001/Accepted: 26 February 2002 The authors would like to thank M. Küchler (IZM Chemnitz) for preparing and performing trench etching process and A. Ostmann (IZM Berlin) for performance of nickel bumping process. This paper was presented at the Conference of Micro System Technologies 2001 in March 2001.     

微创手术式硅微机械加工（MISSM）技术

介绍了一种新颖的微创手术式硅微机械加工(MISSM)技术,该技术充分利用(111)硅片的晶向分布和各向异性湿法腐蚀的特性。通过在单晶硅片表面制作一系列微型释放窗口来定义结构的轮廓及尺寸,实现在单晶硅片内部选择性可自停止腐蚀技术,制作出不同结构尺寸的腔体。同时,结合不同器件结构设计的需求,缝合微型释放窗口并进行后续工艺制作及最终可动结构释放。该技术采用微创手术式单硅片单面体硅工艺替代传统的表面微机械工艺,制作工艺简单,既具有单硅片单面加工的优势又便于与IC工艺兼容。文章详细讲述了微创手术式三维微机械结构的成型机理和工艺流程,并针对其关键技术进行了系统的分析,取得了令人满意的结果。     

Wafer-level reliability characterization for wafer-level-packaged microbolometer with ultrasmall array size

For the development of a small and low-cost microbolometer, wafer-level reliability characterization techniques for vacuum-level packaged wafers are introduced. Amorphous-silicon-based microbolometer-type vacuum sensors fabricated on an 8-inch wafer are bonded with a cap wafer by using an Au–Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity at the wafer level. For a packaged wafer with a membrane thickness below 100 μm, it is possible to determine the hermeticity via a screening test performed using an optical detector. An integrated vacuum sensor having the same structure as a bolometer pixel shows a vacuum level below 100 mTorr. All steps from the packaging process to the fine hermeticity test are implemented at the wafer level to verify that high-volume and low-cost production of the microbolometer is possible.     

Gold metallizations for eutectic bonding of silicon wafers

Gold eutectic bonding of silicon wafers is a good candidate for wafer level vacuum packaging of vibrating MEMS: in this paper we investigated several e-beam evaporated metallizations stacks including a titanium adhesion layer, an optional diffusion barrier (Ni or Pt) and a gold film for eutectic bonding on Si and SiO₂/Si wafers. Interdiffusion in the multilayers for annealing temperatures (380–430°C) larger than the Au–Si eutectic temperature (363°C) and times corresponding to a bonding process was characterized by RBS, roughness and resistivity measurements. Au/Pt/Ti and Au/Ti/SiO₂ were found to have the best characteristics for bonding. This was confirmed by bonding experiments.     

Comparison of etch characteristics of KOH, TMAH and EDP for bulk micromachining of silicon (110)

Bulk micromachining in Si (110) wafer is an essential process for fabricating vertical microstructures by wet chemical etching. We compared the anisotropic etching properties of potassium hydroxide (KOH), tetra-methyl ammonium hydroxide (TMAH) and ethylene di-amine pyro-catechol (EDP) solutions. A series of etching experiments have been carried out using different etchant concentration and temperatures. Etching at elevated temperatures was found to improve the surface quality as well as shorten the etching time in all the etchants. At 120°C, we get a smooth surface (Ra?=?21.2?nm) with an etching rate 12.2???m/min in 40wt% KOH solution. At 125°C, EDP solution (88wt%) was found to produce smoothest surface (Ra?=?9.4?nm) with an etch rate of 1.8???m/min. In TMAH solution (25wt%), the best surface roughness was found to be 35.6?nm (Ra) at 90°C with an etch rate of 1.18???m/min. The activation energy and pre-exponential factor in Arrhenius relation are also estimated from the corresponding etch rate data.