Experiments on postdetection diversity for narrowband digital FMmobile radio

Postdetection diversity, in which the demodulator outputs are weighted in proportion to the vth power of each demodulator input signal envelope when they are added, is described for GMSK signal reception using a frequency demodulator and a one-bit decision feedback equaliser. Experiments on a 16 kbit/s GMSK with a premodulation filter bandwidth-bit duration product of B_bT=0.25, show that using v=2 provides a diversity gain about 1-1.5 dB larger than selection combining, at an average bit error rate of 10^-2 in a Rayleigh fading environment     

Design of a bipolar 10-MHz programmable continuous-time 0.05°equiripple linear phase filter

A bipolar seventh-order 0.05° equiripple linear phase (constant group delay) transconductance-capacitor (g_m-C) low-pass filter with a cutoff frequency (f_c) tunable between 2 and 10 MHz is presented. Programmable equalization up to 9 dB at f_c is also provided. Total harmonic distortion at 2 V_p-p is less than 1%, with a dynamic range equal to 49 dB. Nominal power consumption from a single 5-V supply is 135 mW. The circuit also has a low-power mode (<0.5-mW dissipation)     

New ternary line codes based on trellis structure

The trellis coding technique is applied to line-coded baseband digital transmission systems. For R=n/n+1(n=1,2,3) coding rates, a new codeword assignment model is proposed to accomplish basic requirements for line coding in which each length n binary data sequence is encoded into a length n+1 ternary (+,0,-) line codeword chosen among the code alphabet with 2ⁿ⁺² elements. Assuming Viterbi decoding, the system error performance is improved by increasing the free Euclidean distance between coded sequences. A new algorithm is given for the calculation of the free distance between line-coded sequences so obtained. For R=1/2 and R=3/4 rates, the analytical error performance upper bounds are derived. The power spectral densities of the new line codes are also calculated and compared with those of known line codes     

A high-resolution multibit ΣΔ ADC with digitalcorrection and relaxed amplifier requirements

A second-order multibit ΣΔ (sigma-delta) analog-to-digital converter (ADC) with a 4-b internal quantizer is described. It uses a simple and fast digital correction scheme. A correlated-double-sampling (CDS) fully differential integrator was used, in which the op amp needed only a low slew rate and moderate bandwidth for a sampling rate of 5.25 MHz. A second-order modulator was fabricated in the standard MOSIS p-well 2-μm CMOS process. The excellent measured linearity and high S/(N+D) ratio (95 dB with an oversampling ratio of only 128) of the corrected converter verified the practical advantages of the proposed architecture     

Digital frequency estimation in burst mode QPSK transmission

In burst digital transmission using PSK (phase shift keying) modulation with coherent detection, the recovery of the carrier reference phase and the symbol clock is a key aspect. If all users have a common clock synchronization, symbol timing needs not to be recovered in each burst. A digital processor for carrier recovery without preambles, in the presence of frequency offset, is considered. As an example, a 2 Mb/s QPSK transmission system is considered in which E _b/N_o=10 dB, and the burst and estimation interval length L=15. Using the algorithm described and averaging eight successive estimated frequency offsets, in order to eliminate anomalous errors, the BER (bit error rate) degradation is equal to 0.14 dB when Δf=20 kHz     

Comments on `GMSK with differential phase detection in thesatellite mobile channel'

The error probability results shown by I. Korn (see ibid., vol.38, no.11, p.1980-6, 1990) indicate that the error floor is higher for systems with decision feedback (DF). It was concluded that DF gives a lower error probability only for smaller values of the normalized bandwidth B_tT of the premodulation Gaussian filter, higher values of the ratio of powers in the direct and diffuse signal components K, and a lower range of signal-to-noise ratio. It is shown that this conclusion is not correct by theoretically analyzing the case of the land mobile channel where K=0 (or -∞ dB) and deriving a simple closed-form expression for the error probability for 1 bit differential detection with DF. It is shown that DF reduces the error probability for all values of B_tT and signal-to-noise ratios. The formula derived can be easily evaluated not only for Gaussian minimum shift keying (GMSK) but for all partial-response continuous-phase-modulation (PRCPM) signals     

An 8-b 85-MS/s parallel pipeline A/D converter in 1-μm CMOS

A new architecture consisting of a time-interleaved array of pipelined analog-to-digital converters (ADCs) is presented. A prototype has been designed consisting of four switched-capacitor (S/C) multistage pipelined ADCs in parallel. Hardware cost is minimized by sharing resistor strings, bias circuitry and clock generation circuitry over the array. Digital error correction is employed to ease comparator accuracy requirements. Techniques are employed to minimize the effect of mismatches across the array. A key circuit issue is the design of a high-speed sample-and-hold (S/H) amplifier: a fully differential, mostly NMOS, non-folded-cascode operational-amplifier topology is used. An experimental chip was implemented in 1-μm CMOS and 8-b resolution at a sample rate of 85 megasamples per second (MS/s) was obtained. Signal-to-noise plus distortion (S/(N+D)) was 41 dB for an input sinusoid of 40 MHz     

Performance of time diversity/convolutional coding scheme

A rate R=1/3 coding scheme, comprising a time diversity delay line and an R=2/3 convolutional code, is investigated. The bit error rate performance of the scheme on a binary symmetric channel and a burst error channel is presented     

A double Nyquist digital product detector for quadrature sampling

A technique for digitally obtaining the in-phase (I) and quadrature (Q) components of an IF signal is presented. Initially, the input bandpass signal is mixed to a carrier frequency that is one-fourth of the sampling rate of a single A/D converter. The digitized bandpass signal is converted into its I and Q components at one-half the A/D sample rate by a digital product detector (DPD) composed of a commutator, two sign alternators, and two FIR fractional-phase interpolator filters. This simple structure can yield image performance that is limited by A/D quantization using relatively low interpolator filter orders and IF bandwidths as large as one-half the sampling rate of the A/D converter. The DPD performs Nyquist limit demodulation of the sampled bandpass signal and, therefore, requires a minimal sampling rate. The theory of operation, an analytic proof, design methodology, and simulated performance results are presented. Simulated results show that -86 dB images can be obtained with 8-tap FIR interpolators and a 12 bit A/D converter. A VLSI implementation is also presented     

Delay analysis of a packet voice multiplexer by the ΣDi/D/1 queue

The performance of a statistical multiplexer whose inputs consist of a superposition of voice packet streams is studied. The delay for such a system is analyzed by solving the ΣD_i/ D/1 queue. The analytic method can be used to find the approximate mean delay for an arbitrarily large number of trunks and the approximate delay distribution when the number of trunks is less than 100. An efficient hybrid simulation of the packet voice multiplexer which can be used to find the delay distribution for a large number of trunks is presented. In addition, easily computable error bounds for the present approximation are provided, and the accuracy of the M/ D/1 approximation is investigated     

A low-loss bandpass filter using electrically coupled high-Q TM01δ dielectric rod resonators

For a TM_01δ mode dielectric rod resonator placed coaxially in a TM₀₁ cutoff circular waveguide, characteristics such as the resonant frequency, its temperature coefficient, the unloaded Q, and the other resonances are discussed on the bases of accurate calculations using the mode-matching method. The results show that this resonator compares favorably with a conventional TE_01δ mode dielectric resonator, particularly for realization of a high unloaded Q. Analytical results also verify that interresonator coupling between these two resonators can be expressed equivalently by a capacitively coupled LC resonant circuit. A four-stage Chebyshev filter having a ripple of 0.035 dB and an equiripple bandwidth of 27 MHz at a center frequency of 11.958 GHz was fabricated using these resonators. Its insertion loss is 0.5 dB, which corresponds to an unloaded Q of 17000, and no spurious response appears in the frequency range below 17 GHz     

Si IC-compatible inductors and LC passive filters

Passive inductors and LC filters fabricated in standard Si IC technology are demonstrated. Q-factors from three to eight and inductors up to 10 nH in the gigahertz range have been realized. Measurements on a five-pole maximally flat low-pass filter give midband insertion loss and -3 dB bandwidth close to the nominal design values of 2.25 dB and 880 MHz     

Integration of high-Q GaAs varactor diodes and 0.25 μmGaAs MESFET's for multifunction millimeter-wave monolithic circuitapplications

Two technologies are demonstrated whereby high-Q, vertical-structure, abrupt-junction varactor diodes are monolithically integrated with 0.25-μm GaAs MESFETs on semi-insulating GaAs substrates for multifunction millimeter-wave monolithic circuit applications. Diodes with various anode sizes have been realized with measured capacitance swings of >2.1:1 from 0 V to -4 V and series resistances of approximately 1 Ω. Diodes having a zero bias capacitance of 0.35 pF have Q's of >19000 (50 MHz) with -4 V applied to the anode. Under power bias conditions, the MESFETs have a measured gain of >6 dB at 35 GHz with extrapolated values for f _t and f_max of 32 GHz and 78 GHz, respectively. Using these technologies, a monolithic Ka-band voltage controlled oscillator (VCO) containing a varactor diode, a 0.25-μm GaAs MESFET, and the usual MMIC passive components has been built and tested. At around 31 GHz, the circuit has demonstrated 60-mW power output with 300 MHz of tuning bandwidth     

I/Q channel reversal correcting properties of anSQPSK Costas loop with integrated symbol synchronization

An integrated-carrier loop/symbol synchronizer, using a digital Costas loop with matched arm filters to demodulate staggered quaternary phase-shift keyed (QPSK) signals, is analyzed. An expression is derived for the S curve, parameterized by bit synchronization error. This result suggests that the demodulator structure offers an inherent I/Q channel reversal correcting capability. Computer simulation results are presented that support this conclusion, and suggest that ambiguity resolution performance depends on the ratio of carrier and synchronization loop bandwidths     

Nonredundant error correction analysis and evaluation ofdifferentially detected π/4-shift DQPSK systems in a combined CCI andAWGN environment

The application of the nonredundant error correction (NEC) technique to the North American and Japanese digital cellular modulation standard, π/4-shift differential quadrature phase shift keying (DQPSK), in a combined additive white Gaussian noise (AWGN) and cochannel interference (CCI) environment is proposed, analyzed, and theoretically evaluated. The performance for NEC receivers with single, double, and triple error correction capability is theoretically analyzed and evaluated. For the CCI, the general model, which includes M statistical independent interferers also employing the π/4-shift DQPSK modulation format, is adopted. The theoretical symbol error probability versus carrier-to-noise ratio have been obtained with M and the carrier-to-interference ratio (C/I) as parameters. The results indicate significant performance improvements over conventional differentially detected systems. Some of the results have been verified by computer simulation. The gains offered by the NEC receivers increase as C/I decreases and/or M increases. Significant error floor reductions have been observed     

On the design and performance of a 6-18 GHz three-tier matrixamplifier

A 3×3 matrix amplifier for the 6-18-GHz frequency band has been developed. Using MESFETs fabricated on VPE (vapor-phase epitaxial) material, gains of G=23.5±0.5 dB with a maximum reflection loss of RL=-10 dB were obtained from 5.2 to 18.7 GHz. Gain improvement to G=29.1±1.1 dB at a worst-case reflection loss of RL=-7.5 dB between 4.6 and 18.3 GHz when MBE (molecular-beam epitaxial) material was used for the MESFETs. In addition to the experimental results, important design considerations, especially in regard to the termination impedances of the idle ports, are discussed     

Noise caused by semiconductor lasers in high-speed fiber-opticlinks

Theoretical and experimental results are presented for the signal-to-noise (S/N) ratio caused by mode partition noise, intensity noise, and reflection-induced noise in optical data links. Under given conditions an additional noise source with a S /N ratio of 20 dB will cause a power penalty of 1 dB in order to maintain a 10^-9 bit error rate. From numerical simulations the authors predict the maximum allowable dispersion in the presence of mode partition noise to be approximately 40% of a clock period. This figure is almost independent of bit rate and laser structure and agrees well with the measurements and with results of other workers. Numerical simulations of a buried-heterostructure and a TJS laser were carried out at four bit rates from 565 Mbit/s to 4.5 Gbit/s and the measurements were done at 2.2 Gbit/s using a TJS laser     

The bandwidth performance of a two-element adaptive array withtapped delay-line processing

The bandwidth performance of a two-element adaptive array with a tapped delay line behind each element is examined. It is shown how the number of taps and the delay between taps affect the bandwidth performance of the array. An array with two weights and one delay behind each element is found to yield optimal performance (equal to that obtained with continuous-wave interference) for any value of intertap delay between zero and T₉₀/B, where T ₉₀ is a quarter-wavelength delay time and B is the fractional signal bandwidth. Delays less that T₉₀ yield optimal performance but result in large array weights. Delays larger than T₉₀/B yield suboptimal signal-to-interference-plus-noise ratio when each element has only two weights. For delays between T₉₀/B and 4T₉₀/B , the performance is suboptimal with only two taps but approaches the optimal if more taps are added to each element. Delays larger than T₉₀/B result in suboptimal performance regardless of the number of taps used     

Input filter design criteria for switching regulators usingcurrent-mode programming

Design criteria are developed for a constant-frequency current-programmed switching DC-to-DC converter with an input filter to ensure stability and prevent performance degradation. The criteria are given in terms of the filter voltage transfer function H_S , output admittance Y_s, and the y-parameter model of the switching converter. The criteria are listed as four inequalities and illustrated graphically. The criteria may be summarized as follows: assuming a converter that satisfies its loop gain T, line-to-output transfer function A_gf , and output impedance Z_of requirement is given, an input filter with H_s and Y_s can be used to attenuate the noise emissions from the converter without adversely affecting the converter if H_s⩽1 (may be relaxed to 3-6 dB), and Y _s is larger than the curves of the graphical illustration, perhaps using 6 dB as a rule-of-thumb minimum separation