一种基于滑窗回溯多标准Viterbi译码器

为满足当前通信系统中存在的多种通信标准要求,提出了一种基于滑窗回溯的多标准Viterbi译码器。与其他Viterbi译码器相比,该译码器在支持任意长度序列译码的基础上,实现了1/2、1/3和1/4三种不同码率的配置,并适配5~9五种可变约束长度。此外,该译码器还具有软判决和硬判决两种判决模式,其中软判决采用8 bit有符号数量化。在对路径度量防溢出及幸存路径管理等模块进行优化后,该译码器能够在不显著增加延迟的前提下,具有更优异的工作性能。实验结果表明,该译码器可以根据设置的参数适用多种通信标准,并得到更好的误码性能。     

2,1,7卷积码Viterbi译码器的一种设计方案

卷积码在通信系统中得到了极为广泛的应用.其中约束长度K=7,码率为1/2和1/3的Odenwalder卷积码已经成为商业卫星通信系统中的标准编码方法.提出了一种(2,1,7)卷积码Viterbi译码器的设计方案,该译码器采用全并行结构的加/比/选模块和回溯法以提高译码速度,重点介绍了幸存路径存储与交换单元的设计与实现.     

第三代移动通信系统中通用高速维特比译码器的设计与实现

本文描述了一种可用于第三代移动通信系统的通用高速维特比译码器的设计与实现.该译码器支持可变码率、可变帧长的译码,具有一定的通用性.同时通过两条流水线并行运算的结构,内部可达到588kbps的最高译码速度.该维特比译码器具有很强的通用性和可移植性,可以方便地运用于第三代移动通信系统和其它许多系统.     

A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-/spl mu/m CMOS

A channel decoder chip compliant with the 3GPP mobile wireless standard is described. It supports both data and voice calls simultaneously in a unified turbo/Viterbi decoder architecture. For voice services, the decoder can process over 128 voice channels encoded with rate 1/2 or 1/3, constraint length 9 convolutional codes. For data services, the turbo decoder is capable of processing any mix of rate 1/3, constraint length 4 turbo encoded data streams with an aggregate data rate of up to 2.5 Mb/s with 10 iterations per block (or 4.1 Mb/s with six iterations). The turbo decoder uses the logMAP algorithm with a programmable logsum correction table. It features an interleaver address processor that computes the 3GPP interleaver addresses for all block sizes enabling it to quickly switch context to support different data services for several users. The decoder also contains the 3GPP first channel de-interleaving function and a post-decoder bit error rate estimation unit. The chip is fabricated in a 0.18-/spl mu/m six-layer metal CMOS technology, has an active area of 9 mm/sup 2/, and has a peak clock frequency of 110.8 MHz at 1.8 V (nominal). The power consumption is 306 mW when turbo decoding a 2-Mb/s data stream with ten iterations per block and eight voice calls simultaneously.     

On the performance of rate 1/2 convolutional codes with QPSK onRician fading channels

Consideration is given to the bit error probability performance of rate 1/2 convolutional codes in conjunction with quaternary phase shift keying (QPSK) modulation and maximum-likelihood Viterbi decoding on fully interleaved Rician fading channels. Applying the generating function union bounding approach, an asymptotically tight analytic upper bound on the bit error probability performance is developed under the assumption of using the Viterbi decoder with perfect fading amplitude measurement. Bit error probability performance of constraint length K=3-7 codes with QPSK is numerically evaluated using the developed bound. Tightness of the bound is examined by means of computer simulation. The influence of perfect amplitude measurement on the performance of the Viterbi decoder is observed. A performance comparison with rate 1/2 codes with binary phase shift keying (BPSK) is provided     

High-performance Viterbi decoder with circularly connected 2-D CNN unilateral cell array

A very-high-performance Viterbi decoder with a circularly connected two-dimensional analog cellular neural network (CNN) cell array is disclosed. In the proposed Viterbi decoder, the CNN cells with nonlinear unilateral connections are implemented with electronic circuits at nodes on a trellis diagram. The circuits are circularly connected, forming a cylindrical shape so that the cells of the last stage are connected to those of the first stage. Unilateral connections guide the information to flow circularly around the cylindrical surface. Such configuration enables the conceptually infinite length of the trellis diagram to be reduced to a circuit of limited size. The analog circuits does not require any analog-digital converters, which is the major cause of high power consumption and the quantization error. With the parallel analog processing structure, its decoding speed becomes very high. Also, the decoding mechanism using triggering wave of the CNN circuit does not require the path memory. Circuits for the proposed structure have been designed with HSPICE. Features of the proposed Viterbi decoder are compared with those of the conventional digital Viterbi decoder.     

基于IP核的Viterbi译码器实现

Viterbi译码器在通信系统中应用非常普遍,针对采用DSP只能进行相对较低速率的Viterbi译码的问题,人们开始采用FPGA实现高速率Viterbi译码。本文首先简单描述了Viterbi译码的基本过程,接着根据Viterbi译码器IP核的特点,分别详细介绍了并行结构、混合结构和基于混合结构的增信删余3种Viterbi译码器IP核的主要性能和使用方法,并通过应用实例给出了译码器IP核的性能仿真。     

Systolic array processing of the Viterbi algorithm

Results on efficient forms of decoding convolutional codes based on the Viterbi algorithm by using systolic arrays are presented. Various properties of convolutional codes are discussed. A technique called strongly connected trellis decoding is introduced to increase the efficient utilization of all the systolic array processors. Issues dealing with the composite branch metric generation, survivor updating, overall system architecture, throughput rate, and computational overhead ratio are also investigated. The scheme is applicable to both hard and soft decoding of any rate b/n convolutional code. It is shown that as the length of the code becomes large, the systolic Viterbi decoder maintains a regular and general interconnection structure as well as moderate throughput rate gain over the sequential Viterbi decoder     

An artificial neural net Viterbi decoder

The Viterbi algorithm is a maximum likelihood means for decoding convolutional codes and has thus played an important role in applications ranging from satellite communications to cellular telephony. In the past, Viterbi decoders have usually been implemented using digital circuits. The speed of these digital decoders is directly related to the amount of parallelism in the design. As the constraint length of the code increases, parallelism becomes problematic due to the complexity of the decoder. In this paper an artificial neural network (ANN) Viterbi decoder is presented. The ANN decoder is significantly faster than comparable digital-only designs due to its fully parallel architecture. The fully parallel structure is obtained by implementing most of the Viterbi algorithm using analog neurons as opposed to digital circuits. Several modifications to the ANN decoder are considered, including an analog/digital hybrid design that results in an extremely fast and efficient decoder. The ANN decoder requires one-sixth the number of transistors required by the digital decoder. The connection weights of the ANN decoder are either +1 or -1, so weight considerations in the implementation are eliminated. This, together with the design's modularity and local connectivity, makes the ANN Viterbi decoder a natural fit for VLSI implementation. Simulation results are provided to show that the performance of the ANN decoder matches that of an ideal Viterbi decoder     

A Viterbi Decoder with Efficient Memory Management

This paper proposes a new architecture for a Viterbi decoder with an efficient memory management scheme. The trace‐back operation is eliminated in the architecture and the memory storing intermediate decision information can be removed. The elimination of the trace‐back operation also reduces the number of operation cycles needed to determine decision bits. The memory size of the proposed scheme is reduced to 1/(5×constraint length) of that of the register exchange scheme, and the throughput is increased up to twice that of the trace‐back scheme. A Viterbi decoder complying with the IS‐95 reverse link specification is designed to verify the proposed architecture. The decoder has a code rate of 1/3, a constraint length of 9, and a trace‐forward depth of 45.     

Bit error probability calculations for convolutional codes withshort constraint lengths on very noisy channels

A technique for estimating convolutional code performance on very noisy channels is considered. Specifically, the performance of short constraint length codes operating near the channel cutoff rate is estimated. Decoding convolutional codes with a sliding window decoder (SWD) are considered. This decoder is an optimal (maximum likelihood) symbol decoder as the window size grows toward infinity, while the Viterbi decoder is the maximum-likelihood sequence estimator. The difference in the decoded BERs (bit error rates) between the two decoders is very small and approaches zero asymptotically as the channel BER decreases. Therefore, an estimate on the decoded BER for the SWD can also be used as an estimate of the decoded BER for Viterbi decoding     

Viterbi decoding of the (63, 57) Hamming code-implementation andperformance results

Use of the Viterbi decoder to decode the (63, 57) Hamming code is considered, Implementation and performance of systematic and nonsystematic codes are addressed. It is shown that a Viterbi decoder for the constraint length seven, rate-½ convolutional code can be used to decode both systematic and nonsystematic (63, 57) Hamming codes, but an additional step is needed to complete the decoding of the systematic code. Bounds and simulation results for postdecoding bit-error probability are given and it is shown that the systematic code performs 0.4 dB better than the nonsystematic code. A heuristic explanation is provided     

On a method of calculating the event error probability of convolutional codes with maximum likelihood decoding (Corresp.)

Maximum likelihood (ML) decoding of short constraint length convolutional codes became feasible with the invention of the Viterbi decoder. Several authors have since upper bounded the performance of ML decoders. A method to calculate the event error probability of an ML decoder for convolutional codes is described.     

BER performance with soft and hard decision decoder for coherentoptical DPSK systems corrupted by phase noise

The performance of coherent optical communication systems is significantly degraded by semiconductor laser phase noise. A rate 1/2, constraint length K=7, convolutional error correcting code with Viterbi decoding is used to improve a 3.5-10 Mbit/s DPSK system. Error correcting coding demonstrates the reduction of the influence of phase noise on BER performance, and significantly lowers the BER floor. Soft decision decoding and hard decision decoding performance is investigated and compared     

A low power turbo/Viterbi decoder for 3GPP2 applications

This paper presents a channel decoder that completes both turbo and Viterbi decodings, which are pervasive in many wireless communication systems, especially those that require very low signal-to-noise ratios. The trellis decoding algorithm merges them with less redundancy. However, the implementation is still challenging due to the power consumption in wearable devices. This research investigates an optimized memory scheme and rescheduled data flow to reduce power consumption and chip area. The memory access is reduced by buffering the input symbols, and the area is reduced by reducing the embedded interleaver memory. A test chip is fabricated in a 1.8 V 0.18-/spl mu/m standard CMOS technology and verified to provide 4.25-Mb/s turbo decoding and 5.26-Mb/s Viterbi decoding. The measured power dissipation is 83 mW, while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block. The power consumption in Viterbi decoding is 25.1 mW in the 1-Mb/s data rate. The measurement shows the power dissipation is 83 mW for the turbo decoding with six iterations at 3.1 Mb/s, and 25.1 mW for the Viterbi decoding at 1 Mb/s.     

A Tightened Upper Bound on the Error Probability of Binary Convolutional Codes with Viterbi Decoding

Tighter upper bounds on the error event and the bit error probabilities, respectively, for maximum-likelihood decoding of binary convolutional codes on the binary symmetric channel are derived from upper bounds previously published by Viterbi [1]. The measured bit error rateP_bfor a constraint length 3 decoder has been plotted versus the channel transition probabilitypand shows close agreement with the improved bound on the bit error probability.     

Novel Viterbi decoder VLSI implementation and its performance

An advanced, high-speed, and universal-coding-rate Viterbi decoder VLSI implementation is presented. Two novel circuit design schemes have been proposed: scarce state transition (SST) decoding and direct high-coding-rate convolutional code generation and variable-rate decoding. SST makes it possible to omit the final decision circuit and to reduce the required path memory length without degrading error probability performance. Moreover, the power consumption of the SST Viterbi decoder is significantly reduced when implemented as a CMOS device. These features overcome the speed limits of high-speed and high-coding-gain Viterbi decoder VLSIs in the rate one-half mode imposed by the thermal limitation. The other Viterbi decoding scheme makes it possible to realize a simple and variable coding-rate forward-error-correction circuit by changing only the branch metric calculation ROM tables. By employing these schemes, high-speed (25-Mb/s) and universal-coding-rate Viterbi decoder VLSIs have been developed     

A convolutional single-parity-check concatenated coding scheme forhigh-data-rate applications

The coding scheme uses a set of n convolutional codes multiplexed into an inner code and a (n,n-1) single-parity-check code serving as the outer code. Each of the inner convolutional codes is decoded independently, with maximum-likelihood decoding being achieved using n parallel implementations of the Viterbi algorithm. The Viterbi decoding is followed by additional outer soft-decision single-parity-check decoding. Considering n=12 and the set of short constraint length K=3, rate 1/2 convolutional codes, it is shown that the performance of the concatenated scheme is comparable to the performance of the constraint length K=7, rate 1/2 convolutional code with standard soft-decision Viterbi decoding. Simulation results are presented for the K=3, rate 1/2 as well as for the punctured K=3, rate 2/3 and rate 3/4 inner convolutional codes. The performance of the proposed concatenated scheme using a set of K=7, rate 1/2 inner convolutional codes is given     

CDMA2000系统中通用高速维特比译码器的设计与实现

本文描述了一种可用于 CDMA2 0 0 0通信系统的通用高速维特比译码器基于 FPGA的设计与实现。该维特比译码器具有通用性和高速性 ,它支持可变码率、可变帧长的译码。同时它采用四个 ACS并行运算的结构 ,译码速度可高达 5 88kbit/s,可以方便地运用于第三代移动通信系统和其它许多系统     

A scarce-state-transition Viterbi-decoder VLSI for bit error correction

A high-speed Viterbi decoder VLSI with coding rate R=1/2 and constraint length K=7 for bit-error correction has been developed using 1.5-/spl mu/m n-well CMOS technology. To reduce both hardware size and power dissipation, a recently developed scarce-state-transition (SST) Viterbi decoding scheme has been utilized. In addition, three-layer metallization and an advanced hierarchical macrocell design method (HMCM) have been adopted to improve packing density and reduce chip size. As a result, active chip area has been reduced by half, compared to the conventional standard cell design method (SCM) with two-layer metallization, and 42 K gates have been integrated on a chip with a die size of 9.52/spl times/10.0 mm/SUP 2/. The VLSI decoder has achieved a maximum data throughput rate of 23 Mb/s with a net coding gain of 4.4 dB (at 10/SUP -4/ bit-error rate). The chip dissipates only 825 mW at a data rate of 10 Mb/s.