Junction capacitance reduction due to self-aligned pocketimplantation in elevated source/drain NMOSFETs

A new advantage of an elevated source/drain (S/D) configuration to improve MOSFET characteristics is presented. By adopting pocket implantation into an elevated S/D structure which was formed by Si selective epitaxial growth and gate sidewall removal, we demonstrate that the parasitic junction capacitance as well as the junction leakage was significantly reduced for an NMOSFET while maintaining its good short channel characteristics. These successful results are attributed to the modification of the boron impurity profile in the deep S/D regions. The capacitance reduction rate, furthermore, was more remarkable as the pocket dose was further increased. This means that the present self-aligned pocket implantation is very promising for future MOSFETs with a very short gate length, where high pocket dosage will be required to suppress the short channel effect     

Short channel characteristics of quasi-single-drain MOSFETs

It is clearly demonstrated that source/drain (S/D) elevation is remarkably effective in suppressing the short channel effect against the shrinkage of gate sidewall spacers in MOSFETs. Even if the gate sidewall width is reduced to as very thin as 15 nm, the short channel effect is effectively suppressed by means of the highly elevated S/D regions (80 nm in the present case), though the characteristics of conventional MOSFETs are drastically degraded. This result is explained in terms of the fact that the serious influence due to the deep S/D implantation is suppressed by the formation of a quasi-single-drain configuration. Furthermore, the parasitic S/D resistance decrease, which will bring about drivability enhancement, was observed for reduction in the sidewall width. These favorable experimental results may indicate the definite necessity of elevated S/D engineering for future ultrashort MOSFETs     

Simultaneous optimization of short-channel effects and junctioncapacitance in pMOSFET using large-angle-tilt-implantation of nitrogen(LATIN)

A widely used halo implant process of counter doping has a tradeoff between the short channel effects and the parasitic junction capacitance. In this letter, we propose a novel drain engineering concept, large-angle-tilt-implantation of nitrogen (LATIN) to improve the short-channel effects without the increase of the junction capacitance in the buried-channel pMOSFET using sub-0.25-μm CMOS technology. We compare the electrical characteristics of devices fabricated using LATIN, a conventional arsenic halo implant process (As HALO), and BF₂⁺ source/drain (S/D) implantation only. The LATIN improves the short-channel effects when compared to the case of BF₂⁺ S/D implant only. In addition, the LATIN reduces junction capacitance by 18% when compared to As HALO. As a consequence, the LATIN is shown to be a drain engineering concept to simultaneously optimize the short-channel effects and junction capacitance. Calibrated two-dimensional simulations confirm the improvement with LATIN     

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.     

A novel elevated source/drain PMOSFET formed by Ge-B/Si intermixing

Driven by strain relaxation, the rapid thermal annealing (RTA) of B-doped Ge on an Si substrate forms graded Si_1-xGe_x layers with B confined inside. Based on this observation of Ge-B/Si intermixing, a novel elevated source/drain (S/D) PMOSFET fabrication process is proposed. The new process consists of three simple steps: (a) selective Ge deposition in S/D regions by conventional LPCVD, (b) B implantation, and (c) RTA for Ge-B/Si intermixing to form S/D extensions to the channel. Fabricated PMOSFETs with sub-100 nm gate lengths display excellent short channel performance     

Nanoscale FinFETs with gate-source/drain underlap

Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.     

Self-align recessed source drain ultrathin body SOI MOSFET

In this letter, a self-aligned recessed source/drain (ReS/D) ultrathin body (UTB) silicon-on-insulator (SOI) MOS technology is proposed and demonstrated. The thick diffusion regions of ReS/D are placed on a recessed trench, which is patterned on the buried oxide and go under the SOI film. The new structure reduces the parasitic S/D resistance without increasing the gate-to-drain Miller capacitance, which is the major advantage over the elevated S/D structure. Fabrication details and experimental results are presented. The scalability of the UTB MOSFETs and the larger design window due to reduced parasitics are demonstrated.     

High drive-current electrically induced body dynamic threshold SOIMOSFET (EIB-DTMOS) with large body effect and low threshold voltage

A novel electrically induced body dynamic threshold metal oxide semiconductor (EIB-DTMOS) is proposed where the body is electrically induced by substrate bias and its high performance is demonstrated by experiments and simulations. EIB-DTMOS achieves a large body effect and a low V_th at the same time. The upper limit of the supply voltage of the EIB-DTMOS is higher than that of a conventional DTMOS, because the forward biased p-n junction leakage current of the EIB-DTMOS is lower. Among several DTMOSs, the accumulation mode EIB-DTMOS shows the highest drive-current at fixed off-current due to a large V_th Shift (or large back gate capacitance) and a suppressed short channel effect     

Fabrication of 50-nm gate SOI n-MOSFETs using novel plasma-doping technique

A plasma-doping technique for fabricating nanoscale silicon-on-insulator (SOI) MOSFETs has been investigated. The source/drain (S/D) extensions of the tri-gate structure SOI n-MOSFETs were formed by using an elevated temperature plasma-doping method. Even though the activation annealing after plasma doping was excluded to minimize the diffusion of dopants, which resulted in a laterally abrupt S/D junction, we obtained a low sheet resistance of 920 /spl Omega///spl square/ by the elevated temperature plasma doping of 527 /spl deg/C. A tri-gate structure silicon-on-insulator n-MOSFET with a gate length of 50 nm was successfully fabricated and revealed suppressed short-channel effects.     

Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs

A planar double-gate SOI MOSFET (DG-SOI) with thin channel and thick source/drain (S/D) was successfully fabricated. Using both experimental data and simulation results, the S/D asymmetric effect induced by gate misalignment was studied. For a misaligned DG-SOI, there is gate nonoverlapped region on one side and extra gate overlapped region on the other side. The nonoverlapped region introduces extra series resistance and weakly controlled channel, while the extra overlapped region introduces additional overlap capacitance and gate leakage current. We compared two cases: bottom gate shift to source side (DG/spl I.bar/S) and bottom gate shift to drain side (DG/spl I.bar/D). At the same gate misalignment value, DG/spl I.bar/S resulted in a larger drain-induced barrier lowering effect and smaller overlap capacitance at drain side than DG/spl I.bar/D. Because of reduced drain-side capacitance, the speed of three-stage ring oscillator of DG/spl I.bar/S, with 20% gate misalignment length (L/sub mis/) over gate length (L/sub g/), or L/sub mis//L/sub g/=20%, was faster than that of two-gate aligned DG-SOI.     

A practical device scheme for designing the dopant profile of source/drain extension region in sub-quarter-micron p-MOSFET's

A practical device scheme for designing sub-0.25 μm p-MOSFET's has been examined with respect to the dopant profile of source/drain (S/D) extension. Though shallow junction was reported to be helpless to reduce short channel effect for devices with the same effective gate length (L_eff), shallow-junction techniques are critically important to the practical device/process design for controlling the overlap of S/D extension with the gate. Adjusting the lateral dopant diffusion of S/D extension by other processes except shallow junction techniques may degrade the process control and the resultant performance for devices of the target gate length. In terms of a practical IC technology for sub-0.25 μm p-MOSFET's, an L_eff value properly smaller than the target gate length should be employed to well control the short channel effect and achieve the driving capability as large as possible. Hence, a scheme that properly adjusts the doping concentration for p-S/D extension formed by a given shallow-junction technique is significantly practical for designing the sub-0.25 μm p-MOSFET's with trade-off between driving capability and short channel effect.     

Modeling of strained CMOS on disposable SiGe dots: Shape impacts on electrical/thermal characteristics

We proposed a new non-planar disposable SiGe dot (d-Dot) MOSFET based on Si-on-nothing technology. The new device concepts’ relies on self-assembled single-crystalline d-Dot. The d-Dot MOSFET is prone to a particularly high strain/stress from the underlaying SiGe 3D islands. We show that more than 50% higher mobilities of electrons can be obtained as indicated by 3D simulations performed throughout the entire fabrication process. Then, fully-depleted SOI MOSFET and d-Dot MOSFET are compared in term of short channel effects, parasitic capacitance effects and self-heating effects.     

Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices With Gate–Source/Drain Underlap

Parasitic gate–source/drain (G–S/D) fringe capacitance in nonclassical nanoscale CMOS devices, e.g., double-gate (DG) MOSFETs, is shown, using two-dimensional numerical simulations, to be very significant, gate bias-dependent, and substantially reduced by a well-designed G–S/D underlap. Analytical modeling of the outer and inner components of the fringe capacitance is developed and verified by the numerical simulations; a BOX-fringe component is modeled for single-gate fully depleted silicon-on-insulator MOSFETs. With the new modeling implemented in UFDG, our process/physics-based generic compact model for DG MOSFETs, UFDG/Spice3 shows how nanoscale DG CMOS speed is severely affected by the fringe capacitance and how this effect can be moderated by an optimal underlap, which yields a good tradeoff between the parasitic capacitance and the S/D resistance.     

Subthreshold parameters of radio-frequency multi-finger nanometer MOS transistors

The subthreshold radio-frequency (RF) characteristics of multi-finger nanoscale MOS transistors were studied by using the measured scattering (s) parameters. Small-signal circuit parameters were determined based on a simplified small-signal equivalent circuit model. We found that besides the source and gate resistances, most of the parameters such as the channel resistance, drain inductance and intrinsic capacitance are found to be significantly different to those in the saturation mode of operation. The subthreshold channel resistance increases and the drain inductance decreases as the finger number increases because of the more significant charge transport along the finger boundaries. In addition, the channel resistance can be governed by the drain-induced barrier lowering in a transistor with very short gate length. The equivalent intrinsic capacitance of the small-signal equivalent circuit is governed by the substrate resistance and capacitance which make the parameter extraction more difficult.     

The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

Structural optimization of SUTBDG devices for low-power applications

In this paper, we investigate the impact of physical structure on the performance of symmetric ultrathin body double-gate devices for low-operating-power (LOP) applications. Devices with regular raised source/drain (S/D) structures have optimal spacer thicknesses governed by a tradeoff between fringing capacitance and series resistance. Expanded S/D structures improve on regular raised S/D structures by slowing down the increases in both fringing capacitance with gate height and series resistance with spacer thickness. The cost is more chip area and process complexity. Pure high-/spl kappa/ gate dielectrics raise the off-state current (I/sub OFF/) due to the fringing field-induced barrier lowering effect. Suppressing the I/sub OFF/ increase requires either a significant reduction in equivalent oxide thickness or a significant shift in gate work function. If the gate work function is tuned to maintain a fixed I/sub OFF/, devices with less abrupt S/D-channel junctions suffer a drive current (I/sub ON/) degradation, and devices with weakly coupling S/D and relatively thick bodies gain improvements in I/sub ON/. The I/sub ON/ of a device with metal S/D is significantly lower than required for LOP applications, if the S/D Schottky barrier height (SBH) is over 200 meV. We also briefly discuss the impact of mobility degradation on this structural optimization.     

Anomalous Gate-Edge Leakage Induced by High Tensile Stress in NMOSFET

Anomalously high gate tunneling current, induced by high-tensile-stress memorization technique, is reported in this letter. Carrier-separation measurement method shows that the increased gate tunneling current is originated from the higher gate-to-source/drain (S/D) tunneling current, which worsens when channel length is getting shorter. Also, the device with enhanced tensile strain exhibits 9% higher gate-to-S/D overlapping capacitance. These data indicate that the anomalously high gate tunneling current could be attributed to the high tensile strain that induces the effects of excessive lightly doped dopant diffusion and higher gate-edge damage. The proposed inference is confirmed by channel hot-electron stress.      

A random noise reduction method for an amorphous siliconphotoconversion layer overlaid CCD imager

A novel random noise reduction (RNR) method, which can reduce random noise generated in a storage diode (SD), has been proposed and evaluated with a cell test element. The RNR cell structure features an RNR transistor with a second storage diode, which is inserted between the SD and a vertical CCD (V-CCD). The RNR transistor controls the transfer channel potential and suppresses the random noise generated in the SD. Net first storage diode capacitance with the RNR transistor can be reduced down to (C_f×C_a)/(C_f+m×C_a ), where C_f is the second storage diode capacitance, C _a is the first storage diode capacitance, and m is the channel potential modulation factor. Experimentally, the RNR cell can reduce the random noise in the SD from 42 electrons [r.m.s.] down to 18 electrons [r.m.s.] for the SD capacitance of 5 fF. This makes it possible for the photoconversion layer overlaid CCD imager with the RNR cells to reproduce video images with a high S/N ratio     

Independently driven DG MOSFETs for mixed-signal circuits: part I-quasi-static and nonquasi-static channel coupling

The two tightly coupled channels in independently driven double-gate (IDDG) MOSFET offer new opportunities in constructing mixed-signal circuit modules. Understanding of channel coupling in various bias and frequency regimes is imperative to conceptualize the circuit design and optimization. In Part I, we will investigate both quasi-static and nonquasi-static channel coupling in IDDG through capacitance simulation. The charge reshuffling between channels provides effective coupling at high frequency when source/drain (S/D) carriers cannot respond spontaneously to the applied gate signals, which opens up new high-frequency circuit possibilities beyond the S/D transit time set by the lithography limit. The bias and frequency regions that enhance channel coupling are identified. The transition frequency related to channel charge reshuffling is investigated for its dependence on device geometry. Operational principles and practical limitations are discussed. In Part II, we will present the circuit design examples based on the interchannel coupling.     

太赫兹InP HEMT器件的建模

采用减小栅长(Lg)的方法可以显著提高磷化铟基高电子迁移率晶体管(InP HEMT)器件的直流和微波性能,并使器件的工作频率上升到太赫兹频段。采用T形栅工艺制备了70 nm栅长的InP HEMT器件,器件的直流跨导达到了2.87 S/mm,截止频率ft和最大振荡频率fmax分别为230 GHz和310 GHz。对器件的寄生参数进行了提取和去嵌入,得到了器件的本征S参数。采用经典的9参数模型拓扑结构对器件进行了小信号建模,模型仿真与测试结果拟合良好。针对电流的短沟道效应,采用电流分段的方法来拟合I-V曲线,取得了较好的拟合结果。最后采用Angelov模型对器件的电容进行建模,并最终建立了器件的大信号模型。