On the Use of Static Temperature Measurements as Process Variation Observable

In this paper we present the use of static temperature measurements as process variation observable. Contrary to previously published thermal testing methods, the proposed methodology does not need an excitation signal, thus reducing test cost and improving built-in capabilities of thermal monitoring. The feasibility of the technique and a complete test methodology is presented using a narrowband LNA as example. Finally, a complete electro-thermal co-simulation test bench between the LNA and a differential temperature sensor embedded in the same silicon die is presented in order to validate the results. Results prove that RF figures of merit can be extracted from DC temperature measurements done without loading or exciting the RF circuit under test.     

A method for heat flow resistance measurements in avalanche diodes

Avalanche transit time oscillators are operating at power densities approaching 10⁶W/cm², unprecedented in semiconductor device history. At such power densities, heat flow resistance problems at the interface between the flip-chip mounted silicon chips and the metal substrate, as well as between the package and the heat sink, are extremely critical. This paper describes a new, nondestructive and accurate method of measuring the heat flow resistance between junction and heat sink by utilizing the temperature dependent breakdown voltage Vb(T) as a conveniently built-in temperature sensor. Variations in junction temperature ΔT with power ΔP= VbΔI are, therefore, related to variations in breakdown voltage ΔVbwith current ΔI resulting in a contribution to the electrical small signal resistance of the diode. This thermal resistance contribution Rthcan be separated readily from spreading and space charge resistance Rapand Rscbecause of the frequency dependence of Rth(ω). Furthermore, the frequency dependence of Rth(ω) allows the separation of heat flow resistance contributions originating in the immediate vicinity of the junction (Si-metal interface) from contributions originating at a poor thermal contact between package and heat sink. In keeping with calculations on simplified geometrical configurations, for which analytical solutions of the frequency dependent heat flow in a distributed circuit could be obtained, experimental results are presented which indicate that both heat flow resistance contributions can be extracted and separated with sufficient accuracy from as few as three electrical resistance measurements, e.g., at dc, 100 Hz, and 1 MHz. The simplicity of such measurements and their evaluation make this technique ideal for in-line testing of production devices.     

Wide Dynamic Range CMOS Amplifier Design for RF Signal Power Detection via Electro-Thermal Coupling

A differential temperature sensor for on-chip signal and DC power monitoring is presented for built-in testing and calibration applications. The amplifiers in the sensor are designed with class AB output stages to extend the dynamic range of the temperature/power measurements. Two high-gain amplification stages are used to achieve high sensitivity to temperature differences at points close to devices under test. Designed in 0.18 μm CMOS technology, the sensor has a simulated sensitivity that is tunable up to 210 mV/°C with a corresponding dynamic range of 13 °C. The sensor consumes 2.23 mW from a 1.8 V supply. A low-power version of the sensor was designed that consumes 1.125 mW from a 1.8 V supply, which has a peak sensitivity of 185.7 mV/°C over a 8 °C dynamic range.     

A differential built-in current sensor design for high-speed IDDQtesting

A new built-in current sensor design for IDDQ testing is presented in this paper. Our design overcomes performance limitations encountered by previous sensors by using a novel differential architecture which allows early and accurate detection of abnormal quiescent current following the switching transient. This differential design also naturally compensates for inaccuracies due to any build up of leakage currents and subthreshold conduction effects when relatively large circuit partitions are tested. A test circuit utilizing the sensor in a built-in self-test environment has been fabricated. At clock speeds of up to 31.25 MHz the sensor accurately detects all six of the defects that were implanted in the test chip. SPICE3 simulations of the circuit indicate that with careful design, this sensor can accurately detect faults at operational speeds in a variety of situations     

Ultra-low-power series voltage regulator for passive RFID transponders with subthreshold logic

A series voltage regulator for long-distance passive microwave RFID (RadioFrequency IDentification) transponders, based on subthreshold CMOS circuits, is presented. It is shown that for a voltage regulator that supplies power to subthreshold circuits, temperature compensation would actually represent a disadvantage, while a proper built-in nonzero temperature coefficient can strongly suppress the temperature dependence of the overall subthreshold circuit performance. Implementation and experimental results are discussed     

Some Critical Materials and Processing Issues in SiC Power Devices

There has been a rapid improvement in SiC materials and power devices during the last few years. However, the materials community has overlooked some critical issues, which may threaten the emergence of SiC power devices in the coming years. Some of these pressing materials and processing issues will be presented in this paper. The first issue deals with the possibility of process-induced bulk traps in SiC immediately under the SiC/SiO₂ interface, which may be involved in the reduction of effective inversion layer electron mobility in SiC metal–oxide–semiconductor field-effect transistor (MOSFETs). The second issue addresses the effect of recombination-induced stacking faults (SFs) in majority carrier devices such as MOSFETs, Schottky diodes, and junction field-effect transistors (JFETs). In the past it was assumed that the SFs only affect the bipolar devices such as PiN diodes and thyristors. However, most majority carrier devices have built-in p–n junction diodes, which can become forward biased during operation in a circuit. Thus, all high-voltage SiC devices are susceptible to this phenomenon.     

Fast CMOS ECL receivers with 100-mV worst-case sensitivity

CMOS emitter-coupled logic (ECL) receiver circuits consisting of a differential-amplifier stage and a CMOS inverter are shown to convert 100-mV input signals to on-chip CMOS levels even with worst-case parameter variations in a 5-V 1-μm technology. Two different receiver circuits are used to cover a range of power supply options; a third circuit provides a comparison case. The differential amplifiers feature built-in feedback compensation for common-mode parameter variations. The differential input devices are designed with large widths, minimum channel lengths, and an interleaved layout to enhance gain, speed, and margin for differential mismatches. The simplicity of the circuits and the effectiveness of the built-in compensation facilitate analysis. Partitioning and simplifying assumptions are used to thoroughly test the worst case without complex simulations, while providing insight into the design process     

Equivalent circuit of Gunn devices operating in the monostable switching mode

An equivalent circuit describing the switching properties of highly doped Gunn devices is deduced from detailed partial differential computer simulations. The circuit elements can be derived from device measurements or stationary calculations. Transients of devices with arbitrary external circuits are calculated by ordinary differential equations. The resulting switching time, current amplitude, and relaxation processes are in good agreement with the partial differential computer simulations and with experimental data.     

Intra- and inter-temperature measurement BIST for SiP module using digital frequency analyser circuit

A method and a novel circuitry for intra- and inter-chip temperature measurement in a system in a package (SiP) module is presented. The proposed built-in self-test (BiST) system for the SiP module features a newly proposed digital frequency analyser (DFA) that can be used to efficiently discern clock period differences of up to 1 ns. The full digital interface of the DFA enables power and area efficient temperature measurements in an SiP.     

A Composite Circuit Model for NDR Devices in Random Access Memory Cells

Devices exhibiting negative differential resistance (NDR), such as resonant tunneling diodes and Esaki-type diodes, offer the promise of converting a dynamic random access memory (DRAM) cell to operate like a static random access memory cell with potentially lower dynamic power dissipation and faster read and write operations than a conventional DRAM. However, a circuit model that describes the operation of the resulting novel memory cell and is of use for both hand analysis and design, and circuit simulation as has yet been developed due to the non-analytical current-voltage curve of the two NDR devices in the cell. In this paper, a "composite" circuit model is presented that describes the relationship between current and voltage at the common node of connection of the two NDR devices. The composite model is analytical and can easily be implemented in SPICE or any circuit simulator. It is also useful for hand analysis of the read/write performance metrics. Finally, comparisons of composite models are presented     

Electro-thermal characterization of a differential temperature sensor in a 65 nm CMOS IC: Applications to gain monitoring in RF amplifiers

This paper reports on the design solutions and the different measurements we have done in order to characterize the thermal coupling and the performance of differential temperature sensors embedded in an integrated circuit implemented in a 65 nm CMOS technology. The on-chip temperature increases have been generated using diode-connected MOS transistors behaving as heat sources. Temperature measurements performed with the embedded sensor are corroborated with an infra-red camera and a laser interferometer used as thermometer. A 2 GHz linear power amplifier (PA) is as well embedded in the same silicon die. In this paper we show that temperature measurements performed with the embedded temperature sensor can be used to monitor the PA DC behavior and RF activity.     

Analysis of a multilevel multicell switch-mode power amplifier employing the "flying-battery" concept

This paper presents a novel switch-mode power amplifier based on a multicell multilevel circuit topology. The total output voltage of the system is formed by series connection of several switching cells having a low DC-link voltage. Therefore, the cells can be realized using modern low-voltage high-current power MOSFET devices and the DC link can easily be buffered by rechargeable batteries or "super" capacitors to achieve very high amplifier peak output power levels ("flying-battery" concept). The cells are operated in a phase-shifted interleaved pulsewidth-modulation mode, which, in connection with the low partial voltage of each cell, reduces the filtering effort at the output of the total amplifier to a large extent and, consequently, improves the dynamic system behavior. The paper describes the operating principle of the system, analyzes the fundamental relationships being relevant for the circuit design, and gives guidelines for the dimensioning of the control circuit. Furthermore, simulation results as well as results of measurements taken from a laboratory setup are presented.     

Cancellation of second-order intermodulation distortion and enhancement of IIP2 in common-source and common-emitter RF transconductors

In this paper, a biasing technique for cancelling second-order intermodulation (IM2) distortion and enhancing second-order intercept point (IIP2) in common-source and common-emitter RF transconductors is presented. The proposed circuit can be utilized as an RF input transconductor in double-balanced downconversion mixers. By applying the presented technique, the achievable IIP2 of the mixer is limited by the linearity of the switching devices, component mismatches, and offsets. The proposed circuit has properties similar to the conventional differential pair transconductor in that it ideally displays no IM2 distortion. However, the presented circuit is more suitable for operation at low supply voltages because it has only one device stacked between the transconductor input and output. In the conventional differential pair, two devices consume the voltage headroom. The noise performance of the proposed transconductor is similar to the noise performance of the traditional common-source (emitter) and differential pair transconductors at given bias and device dimensions. On the other hand, the third-order intercept point (IIP3) of the presented transconductor is slightly higher than the IIP3 of the differential pair transconductor at given bias. Finally, the proposed circuit can also be employed as a current mirror, the ratio of which is very insensitive to the voltage swings at the gate or base of the current mirrored transistor.     

Design of high-efficiency RF Class-D power amplifier

In this paper, the losses in a Class-D RF switching power amplifier and their frequency dependence are described. The losses analyzed are the switching, conduction, and gate drive losses. A 300 W, 13.56 MHz, Class-D circuit is designed in the traditional manner to illustrate the magnitude of the different types of loss. A circuit using the ZVS equations developed in this paper is designed. An experimental circuit is built using standard IRF540 devices in TO220 packages. That circuit does not meet its performance goals because of the package inductance. A new low inductance half-bridge package is introduced to solve this problem. Techniques for circuit layout and power measurements for RF applications are also presented in the experimental section. A low loss gate drive circuit is also presented using a Class-E circuit to provide the drive power. The experimental results confirm the accuracy of the design equations derived in this paper     

Simulation of wafer-scale GTO thyristors in circuits

A simulation technique that allows the study of large area power devices composed of many outwardly identical elements operating in a realistic power circuit has been developed. Results are presented showing the transient redistribution of current between a pair of GTO thyristor elements during turn-off under the influence of the power circuit. The method is validated by comparing simulated results with experimental measurements. Variations in carrier lifetime. diffusion uniformity, and gate contact position are studied, and they are shown to significantly alter the turn-off performance. Conclusions are drawn concerning the reliability of large area latching power devices with process inhomogeneity     

Temperature effects on output power of piezoelectric vibration energy harvesters

The performance of piezoelectric vibration energy harvesters was studied as a function of environment temperature. The devices fabricated by soft or hard PZTs were used to investigate the effect of material parameters on the thermal degradation of the devices. PZT MEMS device was also prepared and compared with the bulk devices to investigate scaling effect on the thermal degradation. All devices were heated up to 150 °C in an insulating chamber. Output power was estimated by Roundy’s equivalent circuit model and compared with experimental data. The output power of all devices decreased with the increase of the temperature. The output power as a function of temperature can be predicted by the change of piezoelectric coupling coefficient that is proportional to piezoelectric constant and inverse of square root of dielectric constant. Such combined influence on the output power leads to a lower thermal degradation rate of the soft PZT-based device at a lower temperature. For MEMS scale device based on PZT films, temperature dependence of the output power was reduced. This result can be attributed to decreased temperature dependence of dielectric and piezoelectric constants mainly due to constrained domain motions.     

Electro-thermal coupling analysis methodology for RF circuits

In this paper an electro-thermal co-simulation methodology suitable for RF circuits is presented. It circumvents traditional transient simulation drawbacks that arise when signals or magnitudes whose frequencies are separated orders of magnitude are present simultaneously in the simulated circuit. The accuracy of the proposed technique is verified experimentally by comparing simulation and measurements of the thermal coupling between an integrated power amplifier (PA) and a differential temperature sensor embedded in the same silicon die, using a 65 nm CMOS technology.     

Applications of temperature phase measurements to IC testing

This work analyses the applicability of silicon surface temperature phase measurements as a test observable when a device acting as a heat source dissipates a modulated power function. Specifically, this paper considers two different functions: the phase shift of the temperature waveform as a function of frequency and distance, and the slope of the temperature phase shift versus distance as a function of frequency. Different cases are analyzed in order to show the potential of both functions, including experimental results obtained from a specific integrated circuit (IC). The conclusions will show that samples of the phase function can be used to locate devices acting as heat sources, and that the slope function can be used to extract information regarding the heat flow path in the IC, and, therefore, regarding the structure of the IC.     

An 8-bit flash analog-to-digital converter with an array of redundant comparators

The circuit design and the topology of an 8-bit analog-to-digital converter (ADC) are presented. It is shown that the differential nonlinearity can be reduced by using three comparators and a majorizing element for formation of each bit of the thermometric code. Computer simulation and measurements of reference ADC chips fabricated using the UMC 180-nanometer CMOS technology confirmed the operability of the proposed design. A power consumption of 93 mW, an effective number of bits of 5.8, and a differential nonlinearity of 0.03 bits have been obtained