A Comparison of the Performance and Stability of ZnO-TFTs With Silicon Dioxide and Nitride as Gate Insulators

The performance and stability of thin-film transistors with zinc oxide as the channel layer are investigated using gate bias stress. It is found that the effective channel mobility, ON/OFF ratio, and subthreshold slope of the devices that incorporate SiN are superior to those with SiO₂ as the dielectric. The application of positive and negative stress results in the device transfer characteristics shifting in positive and negative directions, respectively. The devices also demonstrate a logarithmic time-dependent threshold voltage shift suggestive of charge trapping within the band gap and the band tails responsible for the deterioration of device parameters. It is postulated that this device instability is partly a consequence of the lattice mismatch at the channel/insulator interface. All stressed devices recover to near-original characteristics after a short period at room temperature without the need for any thermal or bias annealing.     

High-Performance and Low-Temperature-Compatible p-Channel Polycrystalline-Silicon TFTs Using Hafnium-Silicate Gate Dielectric

In this letter, high-performance p-channel polycrystalline-silicon thin-film transistors (TFTs) using hafnium- silicate (HfSiO_x) gate dielectric are demonstrated with low- temperature processing. Because of the higher gate-capacitance density, TFTs with HfSiO_x gate dielectric exhibit excellent device performance in terms of higher I_ON/I_OFF current ratio, lower subthreshold swing, and lower threshold voltage (V_th) albeit with slightly higher OFF-state current. More importantly, the mobility of TFTs with HfSiO_x gate dielectric is 1.7 times that of TFTs with conventional deposited-SiO₂ gate dielectric.     

Electrical Stability of Hexagonal a-Si:H TFTs

In this letter, we study the current-temperature-stress-induced electrical instability of single and multiple hexagonal (HEX) hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) connected in parallel. The influence of the threshold voltage shift of a single HEX TFT on the overall electrical performance of multiple HEX TFTs is discussed. The results indicate that a-Si:H HEX TFTs have an improved electrical stability and a threshold voltage shift linear dependence on a number of connected HEX-TFT units.     

SiN介质薄膜内应力的实验研究

研究了低压化学气相淀积Sin(LPCVD)介质薄膜的内应力,采用XP-2型台阶仪测量了SiN介质薄膜的内应力,通过改变薄膜淀积时的工艺参数,观察了反应气体流量比、淀积温度、反应室压力等因素对SiN薄膜内应力的影响.讨论了应力产生的原因以及随工艺条件变化的机理,通过工艺条件的合理选择逐步优化工艺.     

Dielectric Properties of Porous Reaction-Bonded Silicon Nitride with Different Additives

The influence of additives on the dielectric properties of porous silicon nitride ceramics with 0.6-mm apertures and 56% porosity prepared by reaction sintering has been studied. The results show that high porosity and large apertures in porous silicon nitride ceramics lower the dielectric constant and dielectric loss compared with dense silicon nitride ceramic. α-Si₃N₄ additive is beneficial to decrease the dielectric constant and dielectric loss. Addition of Y₂O₃ and La₂O₃ powders may result in formation of Y-Si-O-N and La-Si-O-N phases, and enhance the volume fraction of β-Si₃N₄ phase. The transition of Y³⁺ and La³⁺ weakly associated ions and vacancies in the Y-Si-O-N and La-Si-O-N systems leads to higher dielectric constant and dielectric loss.

     

Studies on Dielectric Properties of Silicon Nitride at High Temperature

In this paper, the dielectric properties of silicon nitride are studied using the dielectric polarization theories. According to the developed dielectric models, the temperature dependence of dielectric constant and loss of silicon nitride is mainly analyzed. In addition, the impact of Li^＋, K^＋, Ca^2＋, Al^3＋ and Mg^2＋ doping on the dielectric properties of silicon nitride are also estimated.     

使用纳米硅薄膜技术改进现有硅器件的性能

使用PECVD薄膜沉积技术制成的具有新结构特征的纳米硅薄膜(nc-Si∶H)拥有一系列物性.以纳米硅膜为母体研制成异质结二极管,发现它具有一系列优于单晶硅二极管的独特性能.探讨了使用纳米硅薄膜制造的其它硅器件的可能性,如肖特基器件、TFT晶体管等.     

Effect of SiNx Gate Dielectric Deposition Power and Temperature on a-Si:H TFT Stability

The stability of thin-film transistors (TFTs) of hydrogenated amorphous-silicon (a-Si:H) against gate-bias stress is improved by raising the deposition power and temperature of the silicon nitride gate dielectric. We studied the effects of power density between 22 and 110 mW/cm² and temperature between 150degC and 300degC . The time needed to shift the threshold voltage by 2 V varies by a factor of 12 between low power and low temperature, and high power and high temperature. These results highlight the importance of fabricating a-Si:H TFTs on flexible plastic with the SiN_x gate dielectric deposited at the highest possible power and temperature.     

Active Matrix OTFT Display With Anodized Gate Dielectric

A complete process for an active-matrix (AM) organic thin-film transistor (OTFT) polymer dispersed liquid crystal (PDLC) display is presented. Evaporated pentacene is used as semiconductor. The display comprises 64$times$64 pixel, each with a pixel pitch of $({hbox{312.5}} times {hbox{312.5}}) mu{hbox{m}}^2$. The AM display is fabricated with standard photolithographic processes. Since all process temperatures are below 180$^{circ}$C the processes for the AM backplane can be easily transferred to plastic substrates like PEN or PET. Due to the thin anodically oxidized ${hbox{Al}}_2$ ${hbox{O}}_3$ gate dielectric with a thickness of 60 nm and $varepsilon_{rm r}=9$, driving voltages between 10 and 12 V are sufficient. To protect the pentacene against the PDLC, it is encapsulated with sputtered ${hbox{Ta}}_2 {hbox{O}}_5$ layer. After the passivation a field effect mobility of 0.2 ${hbox{cm}}^{2}/{hbox{V}}cdot{hbox{s}}$ is obtained for the OTFTs.      

Control of Interface Traps in HfO2 Gate Dielectric on Silicon

The effects of postdeposition annealing (PDA) on the interface between HfO₂ high-k dielectric and bulk silicon were studied in detail. The key challenges of successfully adopting the high-k dielectric/Si gate stack into advanced complementary metal–oxide–semiconductor (CMOS) technology are mostly due to interfacial properties. We have proposed a PDA treatment at 600°C for several different durations (5 min to 25 min) in nitrogen or oxygen (95% N₂ + 5% O₂) ambient with a 5-nm-thick HfO₂ film on a silicon substrate. We found that oxidation of the HfO₂/Si interface, removal of the deep trap centers, and crystallization of the film take place during the postdeposition annealing (PDA). The optimal PDA conditions for low interface trap density were found to be dependent on the PDA duration. The formation of an amorphous interface layer (IL) at the HfO₂/Si interface was observed. The growth was due to oxygen incorporated during thermal annealing that reacts with the Si substrate. The interface traps of the bonding features, defect states, and hysteresis under different PDA conditions were studied using x-ray photoelectron spectroscopy (XPS), x-ray diffraction (XRD), transmission electron microscopy (TEM), and leakage current density–voltage (J–V) and capacitance–voltage (C–V) techniques. The results showed that the HfO₂/Si stack with PDA in oxygen showed better physical and electrical performance than with PDA in nitrogen. Therefore, PDA can improve the interface properties of HfO₂/Si and the densification of HfO₂ thin films.     

Double-Gate Tunnel FET With High-κ Gate Dielectric

In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO₂, while the subthreshold slope for fixed values of V_g remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an I_on/I_off ratio of more than 2 times 10¹¹ is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.     

NMOS Compatible Work Function of TaN Metal Gate With Erbium-Oxide-Doped Hafnium Oxide Gate Dielectric

This letter demonstrates reduction in effective work function of tantalum-nitride (TaN) metal gate with erbium-oxide-doped hafnium oxide. We report that TaN effective metal-gate work function can be tuned from Si midgap to the conduction band to meet the work-function requirement of NMOSFETs by incorporating ErO in HfO₂ with an equivalent oxide thickness as low as 1.15 nm. Several other lanthanide-oxide doped hafnium oxides show similar characteristics.     

富硅量不同的富硅氮化硅薄膜的光致发光研究

采用等离子体增强化学气相沉积方法(PECVD)，在低衬底温度下制备了系列富硅量不同的富硅氮化硅薄膜。且所有样品分别经过不同温度的退火。通过X射线光电子能谱(XPS)的测试证实了薄膜中硅团簇的存在。对不同富硅量的氮化硅薄膜做了红外和光致发光的比较研究。由不同富硅量薄膜中硅团簇的尺寸变化对发光峰的影响。得出了发光来源于包埋于氮化硅薄膜中由于量子限制效应而使带隙增大了的硅团簇。     

Effect of Channel Width Shortening on the Stability of a-Si:H/nc-Si:H Bilayer Thin-Film Transistors

The static bias-stress-induced degradation of hydrogenated amorphous/nanocrystalline silicon bilayer bottom-gate thin-film transistors is investigated by monitoring the turn-on voltage (V _on) and on-state current (I _on) in the linear region of operation. Devices of constant channel length 10 mum and channel width varying from 3 to 400 mum are compared. The experimental results demonstrate that the device degradation is channel-width dependent. In wide channel devices, substantial degradation of V _on is observed, attributed to electron injection into the gate dielectric, followed by I _on reduction due to carrier scattering by the stress-induced gate insulator trapped charge. With shrinking the channel width down to 3 mum, the device stability is substantially improved due to the possible reduction of the electron thermal velocity during stress or due to the gate insulator quality uniformity over small dimensions.     

THz Waveguide Mixers With NbTiN HEBs on Silicon Nitride Membranes

We describe the design and performance of waveguide mixers at 1.4 THz and 1.9 THz based on NbTiN phonon-cooled hot electron bolometers (HEBs) fabricated on a 2-mum thick Si₃N₄ membrane. The membrane is bonded to a silicon frame in the mixer block using a flip chip process. Simulated RF coupling is compared with experimental results, showing good agreement. Receiver noise temperature measurements show uncorrected values of 1600 K at 1.4 THz and 2100 K at 1.9 THz, both at 1.5GHz intermediate frequency. Device cooling on the membrane seems not to be problematic. The mixers are used in receivers for the Stratospheric Observatory for Infrared Astronomy (SOFIA) [German REceiver At THz frequencies (GREAT)] and the Atacama path finder experiment (APEX) [CO, N⁺, deuterium observations receiver (CONDOR)]     

p-Si TFT栅绝缘层用SiN薄膜的研究

以NH3和SiH4为反应源气体,采用射频等离子体增强化学气相沉积(RF-PECVD)法在多晶硅(p-Si)衬底上沉积了一系列SiN薄膜,并利用椭圆偏振测厚仪、超高电阻-微电流计、C-V测试仪对所沉积的薄膜作了相关性能测试.系统分析了沉积温度和射频功率对SiN薄膜的相对介电常数、电学性能及界面特性的影响.分析表明,沉积温度和射频功率主要是通过影响SiN薄膜中的Si/N比影响薄膜的性能,在制备高质量的p-Si TFT栅绝缘层用SiN薄膜方面具有重要的参考价值.     

Electrical Characteristics of the HfAlON Gate Dielectric With Interfacial UV-Ozone Oxide

In this letter, the electrical properties of a HfAlON dielectric with UV-O₃ interfacial oxide were comprehensively studied and then compared with those of a HfAlON dielectric with interfacial chemical oxide. In the comparison of dielectric characteristics including leakage current density, transconductance, subthreshold swing, saturation drain current, effective electron mobility, and constant voltage stress reliabilities, the results clearly indicate that high-density interfacial UV-O₃ oxide is beneficial in reducing both bulk and interface traps as well as diminishing stress-induced trap generation, and possesses a high potential to be integrated with further high-kappa dielectric applications.     

Analysis on Conductivity of nc—Si：H Films

A conduction channel model is propsed to explain the high conductivity property of nc-Si:H.Detailed energy band diagram is developed based on the analysis and calculation ,and the conductivity of the nc-Si:H was then analysed on the basis of energy band theory.It is assumed that the conductivity of the nc-Si:H stems from two parts:the conductance of the interface,where the transport mechanism is identified as a thermal -assisted tunneling process,and the conductance along the channel around the grain,which mainly determined the high conductivity of the nc-Si:H.The conductivity of nc-Si:H is calculated and compared with the experiment data .The theory is in agreement with the experiment.     

硅衬底注氮方法制备超薄SiO2栅介质

利用栅氧化前在硅衬底内注氮可抑制氧化速率的方法,制得3.4nm厚的SiO2栅介质,并将其应用于MOS电容样品的制备.研究了N+注入后在Si/SiO2中的分布及热退火对该分布的影响;考察了不同注氮剂量对栅氧化速率的影响.对MOS电容样品的I-V特性,恒流应力下的Qbd,SILC及C-V特性进行了测试,分析了不同氧化工艺条件下栅介质的性能.实验结果表明:注氮后的热退火过程会使氮在Si/SiO2界面堆积;硅衬底内注入的氮的剂量越大,对氧化速率的抑制作用越明显;高温栅氧化前进行低温预氧化的注氮样品较不进行该工艺步骤的注氮样品具有更低的低场漏电流和更小的SILC电流密度,但二者恒流应力下的Qbd值及高频C-V特性相近.     

硅衬底注氮方法制备超薄SiO2栅介质

利用栅氧化前在硅衬底内注氮可抑制氧化速率的方法,制得3.4nm厚的SiO2栅介质,并将其应用于MOS电容样品的制备.研究了N 注入后在Si/SiO2中的分布及热退火对该分布的影响;考察了不同注氮剂量对栅氧化速率的影响.对MOS电容样品的I-V特性,恒流应力下的Qbd,SILC及C-V特性进行了测试,分析了不同氧化工艺条件下栅介质的性能.实验结果表明:注氮后的热退火过程会使氮在Si/SiO2界面堆积;硅衬底内注入的氮的剂量越大,对氧化速率的抑制作用越明显;高温栅氧化前进行低温预氧化的注氮样品较不进行该工艺步骤的注氮样品具有更低的低场漏电流和更小的SILC电流密度,但二者恒流应力下的Qbd值及高频C-V特性相近.