Burn—in对CMOS器件电离辐射效应的影响

MOS管或IC在辐照以前,使其在较长时间内（约200h）处于一定的高温（120℃）下并加偏压。这一作用会改变器件对电离辐射的响应。器件会产生更大的N管阈值电压漂移,IC会产生更大的漏电流（一个量级以上）,减小器件的时间参数退化。Burn-in效应具有很重要的辐射加固方面的意义：1）不考虑这个因素会过高估计器件的时间参数的衰退,从而淘汰掉一些可用的器件;2）对IC的静态漏电流估计不足可导致器伯提前失效。     

CMOS缓冲器的时延估算模型

随着集成电路生产工艺的进展，互连线在集成电路设计中的影响越来越大。为了减小互连线的影响，通常在芯片互连中插入缓冲器，但这样做会增加时延。因此，为了精确地对系统进行时延估计，必须对缓冲器的时延进行估算。基于Sakurai的器件模型，提出了一种新的缓冲器时延估算模型。     

Exact frequency dependent complex admittance of the MOS diode including surface states,Shockley-Read-Hall (SRH) impurity effects,and low temperature dopant impurity response

Solutions of prespecified accuracy for an a.c. transmission line model of the semiconductor in the MOS structure have been found. Together with an accurate solution of the d.c. bias problem, exact capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics can be found at any frequency. Shockley-Read-Hall (SRH) centres and surface states have been included in both the d.c. and a.c. solutions. In addition, accurate low temperature dopant impurity response can be studied since the d.c. solution uses full Fermi integrals over arbitrary densities of states with the impurity dopant band treated like an SRH centre for the a.c. solution.In terms of such non equilibrium situations as occur with the application of light or carrier injection by tunneling, the a.c. solution requires active elements in the transmission line model but the transmission line can still be solved to a prespecified accuracy provided an accurate solution of the d.c. bias problem can be found. In this paper the d.c. solution for the case of light induced pair production was done under the assumption of bulk controlled d.c. quasi Fermi level shifts and thus the accuracy of the related a.c. conductance and capacitance solutions is dependent on the reliability of this assumption.The theoretical studies of parameter effects now possible over the complete frequency, temperature, and d.c. bias ranges allow quantitive prediction of most MOS electrical measurements. It is hoped that this will enable MOS experiments to be used more effectively in determination of space charge region phenomena as well as improving interface characterization.     

A TTL programmable logic array and its applications

A logic-in-latch programmable logic array is developed with practical TTL IC's. Performance measures, LSI fabrication, and various digital applications of such high-speed bipolar PLA are illustrated and compared with the existing MOS programmable ROM's.     

MOS工艺工程技术研究

本文阐述了MOS/CMOS工艺工程技术的特点、研究内容和研究方法,对工艺工程技术进行了全面而系统的分析研究,以提高工艺综合水平,加速MOS和CMOS集成电路向高速化高集成化方向发展,并适应多电路品种的科研开发线和生产线的需要。工艺工程技术研究的核心,就是要解决把单项工艺技术与器件技术综合起来,并转化成集成电路产品的过程中所碰到的关键技术问题。它具有一定的系统性,既要遵循科技发展规律,又要遵循经济发展规律。     

Electron-beam-induced-current investigations on MOS and MNOS devices

The transient behavior of the electron beam induced current (EBIC) in MOS and MNOS capacitors was studied for various Si-oxide and Si-nitride preparation and annealing conditions and interpretations of the corresponding SEM-EBIC micrographs are given. Due to the higher radiation hardness of MNOS structures as revealed by HF and quasistatic CV data, appropriate defect imaging without beam artifacts is far more easily achieved in MNOS than in MOS devices, particularly at higher magnifications. The useful application of MNOS structures for defect characterization by EBIC imaging and generation lifetime is demonstrated.     

Modeling MOS VLSI circuits for transient analysis

Modeling plays a significant role in the efficient simulation of VLSI circuits. By simplifying the models used to analyze these circuits, it is possible to perform transient analyses with reasonable accuracy at speeds of one or two orders of magnitude faster than in conventional circuit simulation programs. The author discusses the models that are used in the second-generation MOTIS timing simulator. The methods used have been applied to a wide variety of MOS digital integrated circuits. All MOS transistors are modeled as voltage-controlled current sources using multidimensional tables. The actual currents are computed by approximation using variation-diminishing tensor splines. Nonlinear device capacitances in the circuit are approximated using linear models which are derived from experimental simulations using a circuit simulator. At the subcircuit level, special structures in the circuit are identified automatically by a preprocessor and are modeled using macro-models. Driver-load MOS transistor gates and bootstrapped circuits are examples of these structures. Their modeling is achieved by an experimental process before implementation in the preprocessor. The simplifications in the device and circuit models presented here have provided a significant improvement in the speed of transient analysis for large MOS digital circuits with relatively little loss in accuracy. This has resulted in a viable design verification environment using MOTIS.     

Computer-aided design and characterization of digital MOS integrated circuits

A computer-aided circuit-simulation method is developed to enable the design, characterization, and optimization of MOS integrated circuits. The computation of dc and transient characteristics is done in terms of physical device parameters extracted from processing information and incorporated in an analytical device model. It is demonstrated that any MOS circuit configuration (with its associated series resistances and parasitic devices) can be analyzed in terms of an equivalent inverter. Input-output transfer characteristics are obtained by superposition of the load and transistor I-V characteristics, providing the necessary information for dc > `worst-case' design. A simple device model was used to compute circuit transient response. All the computed characteristics are in good agreement with measurements performed on integrated circuits.     

CMOS device isolation using the selective-etch-and-refill-with-EPI (SEREPI) process

A technique has been developed for forming wells in a silicon substrate for CMOS IC's with an oxide layer providing lateral isolation between adjacent devices. The silicon in the wells is etched; oxide is formed on the sidewalls of the wells; and the wells are refilled with selectively deposited epitaxial silicon. Ring oscillators and submicrometer n- and p-channel MOS transistors have been fabricated using this isolation technique, and special latch-up test structures have been investigated.     

Contactless characterization of semiconductor devices using surfacephotocharge effect

A technique for evaluating electrical properties of semiconductor wafers and devices using the surface photocharge effect caused by laser radiation is proposed. The measurement setup used in the experiments is presented along with some preliminary results. In particular, experimental results are presented for MOS devices on silicon under bias. It is possible to distinguish from the experimental plots the depletion, accumulation, and inversion regions of the device. Information could be obtained from these curves in a manner analogous to CV plots     

Mode Charts for Cylindrical Microwave Resonators (Program Descriptions)

This program calculates, prints, and plots the data for mode charts. Frequency range, cavity parameters, graph size, grid spacing, and required modes are all user specified.     

Numerical analysis of MOS magnetic field sensors

A new method of numerical analysis of MOS magnetic field sensors is described, which is based on a lumped discrete approach and the application of a general-purpose circuit-analysis program. The channel region of the device is represented by a network of identical L-type circuit cells. A cell consists exclusively of conventional MOS devices, independent voltage sources and controlled current sources, while the magnetic field appears as a parameter in some of these devices. The method allows for an accurate two-dimensional numerical analysis of MOS sensors, including effects which have been neglected hitherto, such as transverse current flow and nonuniform charge density across the channel. Numerical results are given for conventional MOS plates, split-drain MOS devices and distributed current source biased MOS Hall plates.     

Experimental characterization of power VDMOS transistors incommutation and a derived model for computer-aided design

The authors present an experimental method for the characterization of MOS power switching transistors that does not involve technological parameters that are not available to designers. The method is based on the time-domain analysis of the commutation performance of the transistor when constant current are injected into its terminals. The analysis of the time-domain waveforms and the knowledge of the internal structure of the MOS devices are sufficient for the evaluation of the transistor capacitances. It is then possible to introduce a simple large-signal model for power MOSFETs that is particularly well suited to the analysis of circuits using the MOS transistor in commutation (e.g., switching power converters or high-efficiency power amplifiers). The authors also present the model implementation in the SPICE 2 program. Comparison between results obtained experimentally and by computer simulation for several circuits confirms the accuracy of the proposed method     

Frequency response of input impedance implies the distribution of discontinuities of a transmission-line system

From the results of input-impedance measurements of a transmission-line system, the location, nature and magnitude of individual reflections can be calculated by using a finite Fourier transform. Resolution depends only on the frequency range. A computer program calculates and plots the distribution of reflections.     

DC characteristic simulation for floating gate neuron MOS circuits

An original approach to DC characteristic SPICE simulation for floating gate neuron MOS circuits is demonstrated. A novel macromodel which calculates the floating gate potential by combining resistances and dependent voltage and current sources is introduced. Utilising this method, DC characteristics for neuron MOS circuits have been confirmed to be successfully simulated using SPICE     

基于砷化镓衬底的集成天线特性分析

介绍一种可以应用在系统集成(SOC)和芯片间通信方面的结构紧凑的平面天线,制造于砷化镓半绝缘衬底上的Z字型印刷偶极子天线由一个微带—共面转换器馈电。同时也介绍了一套测试天线特性的测试系统,测试结果表明进行芯片内部和芯片之间的无线互联是可行的。     

Computer analysis of nonlinear circuits, excluding radiation (CANCER)

CANCER is a reasonably general circuit analysis program especially suited to integrated-circuit simulation. The program provides for the analysis of large circuits in the following four modes of operation: nonlinear d.c., large-signal transient, small-signal a.c., and thermal and shot noise. These subanalysis capabilities are intercoupled appropriately for convenience and efficiency. Internally, CANCER is a very general nodal analysis program that derives its efficiency from the exploitation of sparse matrix, adjoint, and implicit integration techniques.     

SiC MOS interface characteristics

It is well known that SiC can be thermally oxidized to form SiO ₂ layers. And Si MOSFET IC's using thermally grown SiO₂ gate dielectrics are the predominant IC technology in the world today. However the SiC/SiO₂ interface has not been well characterized as was the case for Si MOS in the early 1960's. This paper presents data which for the first time characterizes the SiC/SiO₂ interface and explains one of the previously unexplained abnormalities observed in the characteristics of SiC MOSFET's     

A new compact DC model of floating gate memory cells withoutcapacitive coupling coefficients

This paper presents for the first time a new compact SPICE model of floating gate nonvolatile memory cells capable to reproduce effectively the complete DC electrical behavior in every bias conditions. This model features many advantages compared to previous ones: it is simple and easy to implement since it uses SPICE circuit elements, is scalable, and its computational time is not excessive. It is based on a new procedure that calculates the floating gate voltage without using fixed capacitive coupling coefficients, thus improving the floating gate voltage estimate that is fundamental for the correct modeling of cell operations. Moreover, this model requires only the usual parameters adopted for SPICE-like models of MOS transistors plus the floating gate-control gate capacitance, making it very attractive to industry as the same parameter extraction procedure used for MOS transistors can be directly applied. The model we propose has been validated on E²PROM and flash memory cells manufactured in existing technology (0.35 μm and 0.25 μm) by STMicroelectronics     

Characterization of solar cells by thermal transient testing

The current paper deals with the application of thermal transient testing as a characterization tool for solar modules. Based on the measurement of different samples (concentrator solar cell, single junction silicon solar cell) we prove the applicability of this measurement technique and address some specific issues of the characterization of solar cells by the thermal transient method.From the measurement metrics such as junction-to-base plate thermal resistance and thermal capacitance(s) can be derived and can serve as a basis of a multi domain solar cell model. The used technique also enables us to verify the quality of attachment layers in a solar module allowing fair quality control and reliability analysis of these devices. Finally a method is proposed to regain the data that is covered by the initial electric transient following the power step. This initial electric transient can be high in large surface devices like solar cells, and covers valuable data describing the structure near to the p–n junction. To eliminate this, simulated transients were fitted to the part of the actual measured thermal transient where the electric transient already decayed. This way the part of the thermal transient that was covered by the electric transient can be reconstructed.