The tiling phenomenon in /spl Sigma//spl Delta/ modulation

The theoretical error signal analysis of a sigma-delta (/spl Sigma//spl Delta/) modulator is a difficult problem due to the presence of a nonlinear operation (the amplitude quantization) in a feedback loop. In this paper, new deterministic knowledge on the transfer function of a /spl Sigma//spl Delta/ modulator is established, thanks to some recently observed properties of its state variables. For a large class of typical /spl Sigma//spl Delta/ modulators with constant inputs, the state variables appear to remain in a tile. We show what characteristics in a /spl Sigma//spl Delta/ modulator are specifically responsible for this property and give some initial proof of it. Under a constant input, the tiling phenomenon has as fundamental consequence that the output is a fixed and memoryless modulo function of n successive integrated versions of the input. This gives the theoretical knowledge that the modulator has an equivalent feedforward circuit expression. We give some immediate theoretical consequences on error analysis including the case of time-varying inputs.     

A time-delay jitter-insensitive continuous-time bandpass /spl Delta//spl Sigma/ modulator architecture

In this paper, we present a new continuous-time bandpass delta-sigma (/spl Delta//spl Sigma/) modulator architecture with mixer inside the feedback loop. The proposed bandpass /spl Delta//spl Sigma/ modulator is insensitive to time-delay jitter in the digital-to-analog conversion feedback pulse, unlike conventional continuous-time bandpass /spl Delta//spl Sigma/ modulators. The sampling frequency of the proposed /spl Delta//spl Sigma/ modulator can be less than the center frequency of the input narrow-band signal.     

Quasi-equivalent feedforward system in asymptotic /spl Sigma//spl Delta/ modulation

It was previously shown that sigma-delta (/spl Sigma//spl Delta/) modulators of "asymptotic" type theoretically yield an equivalent feedforward system where the recursive nonlinear mechanisms are extracted from the feedback loop and reduced to a memoryless function. With time-varying inputs, we show in this paper, partially by mathematical derivations and partially by experiment, that this system is quasi-equivalent to the original modulator in a sense that we explain. This reduction of the nonlinear mechanisms should permit more refined modeling of the /spl Sigma//spl Delta/ errors in future research, with a better account of the original nonlinearities of asymptotic /spl Sigma//spl Delta/ modulation.     

Continuous-time /spl Delta//spl Sigma/ modulators using distributed resonators

We derive a method for using distributed resonators in /spl Delta//spl Sigma/ modulators and demonstrate these /spl Delta//spl Sigma/ modulators have several advantages over existing /spl Delta//spl Sigma/ modulator architectures. Like continuous-time (CT) /spl Delta//spl Sigma/ modulators, the proposed /spl Delta//spl Sigma/ modulators do not require a high-precision track-and-hold, and additionally can take advantage of the high-Q of distributed resonators. Like discrete-time /spl Delta//spl Sigma/ modulators, the proposed /spl Delta//spl Sigma/ modulators are relatively insensitive to feedback loop delays and can subsample. We present simulations of several types of these /spl Delta//spl Sigma/ modulators and examine the challenges in their design.     

A 14-bit high-temperature /spl Sigma//spl Delta/ modulator in standard CMOS

Experimental verification is given for the use of /spl Sigma//spl Delta/ modulation for high-temperature applications (/spl ges/approximately 150/spl deg/C) in a standard CMOS process. Switched-capacitor circuits are used to implement a second-order single-stage and a third-order 2-1 MASH /spl Sigma//spl Delta/ modulator with single-bit quantization. The two modulators have an oversampling ratio of 256 with an input signal bandwidth of 500 Hz. The modulators were fabricated in a 1.5-/spl mu/m standard CMOS technology. A fully differential signal path and near minimum sized switches are used to mitigate the effect of large junction-to-substrate leakage current present at high temperatures. Experimental results show both modulators are capable of over 14 bits of resolution at 225/spl deg/C and over 13 bits of resolution at 255/spl deg/C. Results show that the single-stage modulator is more resistant to high-temperature circuit impairment than is the MASH cascaded structure.     

Tunable continuous-time bandpass /spl Sigma//spl Delta/ modulators with fractional delays

An analytical design methodology for continuous-time (CT) bandpass (BP) /spl Sigma//spl Delta/ modulators is presented. Second- and fourth-order tunable continuous time BP /spl Sigma//spl Delta/ modulator design equations are presented. A novel /spl Sigma//spl Delta/ loop architecture, where the traditional CT BP loop filter function is replaced with the filter function with fractional delays, is proposed. Validity of the methodology is confirmed by mixed-signal behavioral simulations.     

High-order electromechanical /spl Sigma//spl Delta/ modulation in micromachined inertial sensors

Analysis of second-order electromechanical sigma-delta (/spl Sigma//spl Delta/) inertial sensors shows that in-band quantization error introduces a resolution penalty, which cannot be eliminated by oversampling. In addition, a tradeoff between resolution and phase compensation forces such systems to operate with reduced phase margin. This paper introduces high-order electromechanical /spl Sigma//spl Delta/ modulation as an approach, which eliminates the quantization noise overhead and allows for increased phase compensation without degrading the resolution. Quasi-linear analysis is used to evaluate the contribution of the individual noise sources to the output of the system and to examine the effect of noise interaction on the behavior of electromechanical /spl Sigma//spl Delta/ modulators.     

Adaptive order reduction scheme for high-order single-bit /spl Delta//spl Sigma/ Modulators

A scheme for achieving adaptive reduction in the order of the loop filter of usual high-order, single-stage, single-bit Delta-Sigma (/spl Delta//spl Sigma/) modulators is proposed in order to improve their performance. The resulting /spl Delta//spl Sigma/ modulators can recover from instability effectively, having also an extended input signal range in comparison to that of the corresponding conventional /spl Delta//spl Sigma/ modulators.     

Hybrid /spl Sigma//spl Delta/ modulators with adaptive calibration

This paper describes an architecture for stable high-order /spl Sigma//spl Delta/ modulation. The architecture is based on a hybrid /spl Sigma//spl Delta/ modulator, wherein hybrid integrators replace conventional analog integrators. The hybrid integrator, which is a combination of an analog integrator and a digital integrator, offers an increased dynamic range and helps make the resulting high-order /spl Sigma//spl Delta/ modulator stable. However, the hybrid /spl Sigma//spl Delta/ modulator relies on precise matching of analog and digital paths. In this paper, a calibration technique to alleviate possible mismatch between analog and digital paths is proposed. The calibration adaptively adjusts the digital integrators so that their transfer functions match the transfer functions of corresponding analog integrators. Through behavioral-level simulations of fourth-order /spl Sigma//spl Delta/ modulators, the calibration technique is verified.     

A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth

This paper presents the first implementation results for a time-interleaved continuous-time /spl Delta//spl Sigma/ modulator. The derivation of the time-interleaved continuous-time /spl Delta//spl Sigma/ modulator from a discrete-time /spl Delta//spl Sigma/ modulator is presented. With various simplifications, the resulting modulator has only a single path of integrators, making it robust to DC offsets. A time-interleaved by 2 continuous-time third-order low-pass /spl Delta//spl Sigma/ modulator is designed in a 0.18-/spl mu/m CMOS technology with an oversampling ratio of 5 at sampling frequencies of 100 and 200 MHz. Experimental results show that a signal-to-noise-plus-distortion ratio (SNDR) of 57 dB and a dynamic range of 60 dB are obtained with an input bandwidth of 10 MHz, and an SNDR of 49 dB with a dynamic range of 55 dB is attained with an input bandwidth of 20 MHz. The power consumption is 101 and 103 mW, respectively.     

IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator for digital receiver applications

Bandpass modulators sampling at high IFs (/spl sim/200 MHz) allow direct sampling of an IF signal, reducing analog hardware, and make it easier to realize completely software-programmable receivers. This paper presents the circuit design of and test results from a continuous-time tunable IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator implemented in InP HBT IC technology for use in a multimode digital receiver application. The bandpass /spl Delta//spl Sigma/ modulator is fabricated in AlInAs-GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 130 GHz and a maximum frequency of oscillation (f/sub MAX/) of 130 GHz. The fourth-order bandpass /spl Delta//spl Sigma/ modulator consists of two bandpass resonators that can be tuned to optimize both wide-band and narrow-band operation. The IF is tunable from 140 to 210 MHz in this /spl Delta//spl Sigma/ modulator for use in multiple platform applications. Operating from /spl plusmn/5-V power supplies, the fabricated fourth-order /spl Delta//spl Sigma/ modulator sampling at 4 GSPS demonstrates stable behavior and achieves a signal-to-(noise + distortion) ratio (SNDR) of 78 dB at 1 MHz BW and 50 dB at 60 MHz BW. The average SNDR performance measured on over 250 parts is 72.5 dB at 1 MHz BW and 47.7 dB at 60 MHz BW.     

A triple-mode continuous-time /spl Sigma//spl Delta/ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver

Time jitter in continuous-time /spl Sigma//spl Delta/ modulators is a known limitation on the maximum achievable signal-to-noise-ratio (SNR). Analysis of time jitter in this type of converter shows that a switched-capacitor (SC) feedback digital-to-analog converter (DAC) reduces the sensitivity to time jitter significantly. In this paper, an I and Q continuous-time fifth-order /spl Sigma//spl Delta/ modulator with 1-bit quantizer and SC feedback DAC is presented, which demonstrates the improvement in maximum achievable SNR when using an SC instead of a switched-current (SI) feedback circuit. The modulator is designed for a GSM/CDMA2000/UMTS receiver and achieves a dynamic range of 92/83/72 dB in 200/1228/3840 kHz, respectively. The intermodulation distance IM2, 3 is better than 87 dB in all modes. Both the I and Q modulator consumes a power of 3.8/4.1/4.5 mW at 1.8 V. Processed in 0.18-/spl mu/m CMOS, the 0.55-mm/sup 2/ integrated circuit includes a phase-locked loop, two oscillators, and a bandgap.     

A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth

This paper presents the design and experimental results of a continuous-time /spl Sigma//spl Delta/ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time /spl Sigma//spl Delta/ modulators is solved by our proposed architecture. A prototype third-order continuous-time /spl Sigma//spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 /spl times/ 2.4 mm/sup 2/. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.     

Numerical method for determining the quantization error PDF of single-bit /spl Sigma//spl Delta/ Modulators

Existing models for the quantizer of /spl Sigma//spl Delta/ modulators make assumptions on the probability density function (pdf) of the quantization error, or some other convenient signal of the modulator. In this paper, a method for the determination of this pdf for single-bit /spl Sigma//spl Delta/ modulators is presented. First, a numerical method is proposed in order to solve the simplified equation for the quantization error pdf for first-order systems considering noiseless and noisy dc input signals. Then, it is shown how most practical high-order (>2)/spl Sigma//spl Delta/ modulators, resulting from well-established design methods, can be modeled as first-order systems plus an additive noise source at the input. Hence, their quantization error pdf is analyzed using the proposed method. Simulation results are shown to be in considerable agreement with those of the proposed method.     

A low-power multi-bit /spl Sigma//spl Delta/ modulator in 90-nm digital CMOS without DEM

Multi-bit sigma-delta modulators are widely used in analog-to-digital conversion especially in the modern deep-submicron CMOS process. As the quantizer resolution of /spl Sigma//spl Delta/ modulators increases, the SNR performance improves. However, the feedback DAC has to maintain high linearity. The general practice to achieve that is to use dynamic element matching (DEM). The methodology proposed in this paper will greatly reduce the complexity or even avoid usage of DEM for multi-bit /spl Sigma//spl Delta/ modulators. The proposed methodology-truncation error shaping and cancellation-reduces the feedback DAC levels for multi-bit quantizers. A prototype was designed in a standard CMOS 90-nm process to demonstrate the proposed methodologies. It achieved targeted performance without DEM at low power consumption with small silicon area.     

Hexagonal /spl Sigma//spl Delta/ modulators in power electronics

Design techniques for /spl Sigma//spl Delta/ modulators from communications are applied and adapted to improve the spectral characteristics of high frequency power electronic applications. A high frequency power electronic circuit can be regarded as a quantizer in an interpolative /spl Sigma//spl Delta/ modulator. We review one dimensional /spl Sigma//spl Delta/ modulators and then generalize to the hexagonal sigma-delta modulators that are appropriate to three-phase converters. A range of interpolative modulator designs from communications can then be generalized and applied to power electronic circuits. White noise spectral analysis of sigma-delta modulators is generalized and applied to analyze the designs so that the noise can be shaped to design requirements. Simulation results for an inverter show significant improvements in spectral performance.     

A vertically integrated tool for automated design of /spl Sigma//spl Delta/ modulators

We present a tool that starting from high-level specifications of switched-capacitor (SC) /spl Sigma//spl Delta/ modulators calculates optimum specifications for their building blocks and then optimum sizes for the block schematics. At both design levels, optimization is performed using statistical techniques to enable global design and innovative heuristics for increased computer efficiency as compared with conventional statistical optimization. The tool uses an equation-based approach at the modulator level, a simulation-based approach at the cell level, and incorporates an advanced /spl Sigma//spl Delta/ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: (1) a 16 b @ 16 kHz output rate second-order /spl Sigma//spl Delta/ modulator; and (2) a 17 b @ 40 kHz output rate fourth-order /spl Sigma//spl Delta/ modulator. Both use SC fully differential circuits and were designed using the proposed tool and manufactured in a 1.2 /spl mu/m CMOS double-metal double-poly technology.<>     

A bandpass mismatch noise-shaping technique for /spl Sigma/-/spl Delta/ Modulators

A simple bandpass mismatch noise-shaping technique for /spl Sigma/-/spl Delta/ modulators is presented. This technique uses the data-directed scrambler structure and achieves /spl sim/20 dB improvement in signal-to-noise ratio (SNR) for an oversampling ratio (OSR) of 32. Compared to the technique of bandpass mismatch noise shaping of Lin and Schreier, here, the SNR is improved by /spl sim/ 7dB resulting in a 1-bit improvement in resolution. The selection logic is half the size of the logic in Lin and Schreier and is fully compatible with the low-pass selection logic of Kwan et al.. This compatibility allows implementation of bandpass/low-pass modulator as a single product.     

Design of double-sampling /spl Sigma//spl Delta/ modulation A/D converters with bilinear integrators

Double-sampling techniques allow to double the sampling frequency of a switched capacitor /spl Sigma//spl Delta/ analog-to-digital convertors without increasing the clock frequency. Unfortunately, path mismatch between the double sampling branches may cause noise folding, which could ruin the modulator's performance. The fully floating double-sampling integrator is an interesting building block to be used in such a double sampling /spl Sigma//spl Delta/ modulator because its operation is tolerant to path mismatch. However, this circuit exhibits an undesired bilinear filter effect. This effectively increases the order of the modulator by one. Due to this, previously presented structures don't have enough freedom to fully control the modulator pole positions. In this paper, we introduce modified topologies for double-sampling /spl Sigma//spl Delta/ modulators built with bilinear integrators. We show that these architectures provide full control of the modulator pole positions and hence can be used to implement any noise transfer function. Additionally, analytical expressions are obtained for the residual folded noise.     

A 3.3-mW /spl Sigma//spl Delta/ modulator for UMTS in 0.18-/spl mu/m CMOS with 70-dB dynamic range in 2-MHz bandwidth

A quadrature fourth-order, continuous-time, /spl Sigma//spl Delta/ modulator with 1.5-b quantizer and feedback digital-to-analog converter (DAC) for a universal mobile telecommunication system (UMTS) receiver chain is presented. It achieves a dynamic range of 70 dB in a 2-MHz bandwidth and the total harmonic distortion is -74 dB at full-scale input. When used in an integrated receiver for UMTS, the dynamic range of the modulator substantially reduces the need for analog automatic gain control and its tolerance of large out-of-band interference also permits the use of only first-order prefiltering. An IC including an I and Q /spl Sigma//spl Delta/ modulator, phase-locked loop, oscillator, and bandgap dissipates 11.5 mW at 1.8 V. The active area is 0.41 mm/sup 2/ in a 0.18-/spl mu/m 1-poly 5-metal CMOS technology.