An analog front end for 2400-bit/s split-band full-duplex modems

An analog front-end LSI for 1200/2400 full-duplex modems which conform to CCITT V.22. and Bell 212A is described. The chip includes A/D and D/A converters, bandlimiting filters, delay equalizers, AGC circuit, tone generator, multipurpose low-pass filter, and voltage reference generator. The chip is fabricated by a 5-/spl mu/m CMOS process, and chip size is 6.50 mm/spl times/6.37 mm. The circuit operates from +5.0-V and -5.0-V power supplies. Typical power consumption is 100 mW.     

A single-chip CMOS analog/digital mixed NTSC decoder

A single-chip CMOS LSI that integrates all analog-to-digital (A/D), digital-to-analog (D/A), peripheral, and digital signal processing circuits necessary for a digital National Television System Committee (NTSC) signal decoder is described. The LSI chip accepts composite NTSC video signals in analog form, digitizes them using the on-chip A/D converter, converts them to component RGB signals, and then converts the signals to analog form by using the on-chip D/A converters. The development of circuits that maximize use of the input digital data is discussed. A 6-b A/D circuit is used to reduce the circuit size. Circuits that help maintain acceptable picture quality despite 6-b resolution were developed. Besides analog NTSC signal input and RGB signal output, the IC can also input and output digital NTSC signals, Y/C (luminance, chrominance) signals, and RGB signals. Applications of the LSI are presented     

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-/spl mu/m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 /spl mu/A/sub rms/. The input sensitivity of the receiver front-end is 16 /spl mu/A for 2.5-Gbps operation with bit-error rate less than 10/sup -12/, and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 /spl mu/m/spl times/1500 /spl mu/m.     

An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip

A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order /spl Sigma//spl Delta/ modulator with 3.8-/spl mu/Vrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 /spl mu/W, respectively, at a single 0.9-V supply. The core area is 0.5 mm/sup 2/ in a 0.25-/spl mu/m standard CMOS technology.     

A CMOS line equalizer for a digital subscriber loop

An adaptive line equalizer for a 200-kb/s digital subscriber loop is developed in the form of a monolithic LSI and implemented using 2.5-/spl mu/m CMOS technology. Most analog portions consist of switched-capacitor circuits successfully designed to minimize power consumption, the amount of hardware, and off-chip components. The main features of the LSI equalizer are an /spl radic/f step equalizer, a five-tap decision-feedback equalizer using /spl Delta/M D/A conversion, a newly developed wave difference method (WDM), tankless timing extraction PLL, and a line driver. Consequently, the LSI can equalize a 52-dB line loss with four bridge taps; it dissipates only 67 mW, and the chip area is 5.7/spl times/5.9 mm/SUP 2/.     

An ISDN echo-cancelling transceiver chip set for 2B1Q coded U-interface

A three-chip set for a 2B1Q U-interface transceiver has been developed. The chip set is composed of an analog front-end (AFE), echo-canceller (EC), and receiver (RCV) LSIs. The AFE LSI includes a 12-b accuracy oversampling analog/digital converter. The EC and RCV LSIs are 26- and 16-bit microprogrammable digital signal processors, respectively. A digital phase-locked loop is used to minimize the analog part. Residual echo increase by a timing phase jump is compensated for by a newly introduced additional adaptive filter. Infinite impulse response filters and multiresponse filters reduce the necessary number of taps for both the echo canceller and the decision-feedback equalizer. The AFE and the two digital signal processor LSIs are implemented in 1.6- and 1.2-μm double-metal layer CMOS processes, respectively. A 6-km loop coverage was realized with a less than 10^-7 error rate. Total power consumption by the chip set is 580 mW at 5-V single supply     

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags in conformance with ISO/IEC 18000-3 protocol

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags is presented in this paper. The design of the RF analog front-end and digital control is based on ISO/IEC 18000-3 MODE 1 protocol. This paper mainly focuses on RF analog front-end circuits. In order to supply voltage for the whole tag chip, a high efficiency power management circuit with a rather wide input range is proposed by utilizing 15.5 V high voltage MOS transistors. Furthermore, a high sensitivity, low power consumption 10% ASK demodulator with a subthreshold-mode hysteresis comparator is introduced for reader-to-tag communication. The tag chip is fabricated in 0.18-μm 2-poly 5-metal mixed signal CMOS technology with EEPROM process. An on-chip 1 kb EEPROM is used to support tag identification, data writing and reading. The core size of the analog front-end is only 0.94×0.84 mm² with a power consumption of 0.42 mW. Measured results show that the power management circuit is able to maintain a proper working condition with an input antenna voltage range of 5.82–12.3 V; the maximum voltage conversion ratio of the rectifier reaches 65.92% when the tag antenna voltage is 9.42 V. Moreover, the power consumption of the 10% ASK demodulator is only 690.25 nW.     

A CMOS automatic line equalizer LSI chip using active-RC filtering

Using digitally controlled RC-active filtering and a new digital circuit configuration, a CMOS automatic line equalizer LSI has been developed for a digital transmission system. This LSI can automatically equalize line losses of up to 42 dB with 0.2 dB precision even with bridged tap echoes up to two time slots away from the signal pulses, at a transmission rate of up to 200 kb/s. The chip size of 7.0/spl times/7.0 mm is realized through optimized circuit design and double polysilicon CMOS technology. The circuit design concept that permits high-speed operation with high precision and the characteristics of the fabricated LSI are described.     

An analog CMOS autopilot

Results are presented of an analog LSI CMOS missile autopilot. The autopilot is a two-chip set which requires a total area of 210000 sq miles and consumes 700 mW of power. The set is fabricated in a double-poly p-well silicon-gate technology. The chips perform a wide array of analog functions, including precision filtering, full-wave demodulation, digital-to-analog conversion, limiting, pulsewidth modulation, and offset cancellation. A number of digital functions are also provided. The chip set was functionally correct on the first iteration after computer-aided verification. The output noise of the chip set is 6.5 mV, integrated over a bandwidth of 5-500 Hz. Results are presented over a temperature range of -55/spl deg/C to 125/spl deg/C.     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

A single-chip high-voltage shallow-junction BORSHT-LSI

High-voltage and low-voltage BORSHT functions have been successfully incorporated into a single chip for the purpose of realizing a low-cost small-size subscriber-line interface circuit in a digital local switching system. The developed BORSHT-LSI is fabricated using a newly designed 350-V p-n-p-n device with shallow junctions 2 /spl mu/ in depth and a dielectrically isolated complementary bipolar technique. The chip size is 4.25/spl times/6.21 mm, 33% smaller than the already developed RT-LSI and BSH-LSI combined. The worst-case power dissipation is about 600 mW. The LSI can be mounted onto a 40 pin package.     

一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路

提出了一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路.通过引入一个使用亚阈值技术的基准源,电路实现了温度补偿,从而使得系统时钟在～40～100℃的范围内保持稳定.在模块设计中,提出了一些新的电路结构来降低系统功耗,其中包括一种零静态功耗的上电复位电路和一种新的稳压电路.该射频/模拟前端电路采用不带肖特基二极管0.18μm CMOS EEP-ROM工艺流片实现,它与数字基带、EEPROM一起实现了一个完整的标签芯片.测试结果表明,该芯片的最低电源电压要求为0.75V.在该最低电压下,射频/模拟前端电路的总电流为4.6μA.     

A single chip FSK modem

In the development of a fully LSI-designed single-chip 300-b/s asynchronous FSK modem, two `hard to beat' problems are: (1) to build both analog and digital circuits on-chip in-such a way that the modem performance is practically free from line noise and transmission distortion; and (2) to meet the requirement (CCITT V.21) of a +5 dBm level margin to discriminate carrier-on from carrier-off under the rigid operating conditions expected. It was found that a combination of high-gain limiter, digital PLL, and postdetection filter in the demodulator section was useful to solve the first problem. A combination of a stabilized rectifier and voltage reference generator contributed to the solution of the second problem. Measurements on chips indicated at /spl plusmn/12% isochronous distortion in the received signal level range of -5 to -45 dBm, a 10/SUP -5/ bit error rate at an SNR of 3 dB, and /spl plusmn/0.15 dB carrier detection level deviation over the temperature range from -20 to +100/spl deg/C within the supply voltage variations of /spl plusmn/10%. Switched-capacitor filters were used throughout the analog section. The device requires two power supplies, +12 and +5 V. The power consumption is 85 mW, and the chip size is 5.9/spl times/5.4 mm.     

A front-end processor for modems

A front-end processor constructed of an oversampling delta-sigma ADC/DAC (analog-to-digital converter/digital-to-analog converter) and a digital signal processor is described. The chip can handle a maximum of eight different processing modes for modem applications including the echo canceling scheme. The chip incorporates a voltage reference circuit, digital PLL (phase-locked loop), and a unique second interpolation circuit to realize both conventional QAM (quadrature amplitude modulation) demodulation and echo cancel-type demodulation. The chip is fabricated in a 1.5-μm double-poly double-metal CMOS process. The chip size is 9.2 mm×7.2 mm, and the typical power consumption is 150 mW with a single +5.0-V power supply     

CMOS analog front end of a transceiver with digital echocancellation for ISDN

A CMOS analog front-end which contains a novel pulse-shaping circuit, an extremely linear-line-driver state, an oversampling second-order noise-shaping coder, and a wake-up signal detector is discussed. An analog front-end for 4B 3T coded signals is realized in a 2.5-μm CMOS technology and operates up to 4.5 km with 0.4-mm-diameter lines, needing only one 5-V power supply. It is possible to transmit 2B 1Q coded signals also, using a modified pulse-shaping circuit     

A microprogrammable real-time video signal processor (VSP) formotion compensation

A video signal processor (VSP) LSI circuit with a three pipelined architecture has been developed for pattern matching, which is fundamental for the motion compensation necessary for teleconferencing systems. A high-speed arithmetic logic unit with absolute-value calculation capability and a minimum/maximum value detector, which are essential to pattern matching, have been integrated on the VSP LSI. The chip was fabricated with a 2.5-μm CMOS and double-layer metallization technology. The number of MOSFETs integrated on the 9.91×9.50-mm ² chip is about 48000. It operates at a 14.3-MHz clock frequency with a single 5-V power supply and typically consumes 240 mW. An experimental video signal processing system, using a single VSP LSI chip, is discussed     

A 1 GHz CMOS analog front-end for a generalized PRML read channel

A 1 GHz CMOS analog front-end for general partial response maximum likelihood (GPRML) read channel in hard disk drive application has been implemented in 0.35 /spl mu/m CMOS. A continuous time analog filter fulfills the relaxed equalization for GPRML detection and can save up to 35% power consumption for the whole read channel. An analog DFE-based timing recovery loop is implemented to avoid the extremely long latency in the digital signal processing path (Viterbi decoder). The measured performances is 1.1 dB off simulations at 800 MHz and 1.6 dB off at 1GHz. The chip draws 240 mW from a 3.3 V supply at 800MHz clock and 380 mW from a 3.6 V supply at 1 GHz clock.     

A capacitive fingerprint sensor chip using low-temperature poly-Si TFTs on a glass substrate and a novel and unique sensing method

We have developed a capacitive fingerprint sensor chip using low-temperature poly-Si thin film transistors (TFTs). We have obtained good fingerprint images which have sufficient contrast for fingerprint certification. The sensor chip comprises sensor circuits, drive circuits, and a signal processing circuit. The new sensor cell employs only one transistor and one sensor plate within one cell. There is no leakage current to other cells by using a new and unique sensing method. The output of this sensor chip is an analog wave and the designed maximum output level is almost equal to the TFT's threshold voltage, which is 2-3 V for low-temperature poly-Si TFTs. We used a glass substrate and only two metal layers to lower the cost. The size of the trial chip is 30 mm/spl times/20 mm/spl times/1.2 mm and the sensor area is 19.2 mm/spl times/15 mm. The size of the prototype cell is now 60 /spl mu/m/spl times/60 /spl mu/m at 423 dpi, but it will be easy to increase the resolution up to more than 500 dpi. The drive frequency is now 500 kHz and the power consumption is 1.2 mW with a 5-V supply voltage. This new fingerprint sensor is most suitable for mobile use because the sensor chip is low cost and in a thin package with low power consumption.     

A high-speed digital filter LSI for video signal processing

A ninth-order symmetrical filter has been developed for use in two-dimensional (2-D) processing in TV video systems, especially in high-definition TV receivers. A 2-D filter that is composed of only two types of LSIs (one-dimensional (1-D) digital filter LSI and delay-line) is discussed. The architecture of the digital filter LSI and circuit techniques are presented to obtain high-speed operation, to save chip area, and to decrease power consumption. The order and the transfer function of the filter can be altered by means of the external terminals. The chip, achieved through 2-/spl mu/m CMOS technology, contains about 52000 transistors and occupies an area of 50 mm/SUP 2/. It operates at a high clock frequency of over 33 MHz, and dissipates only 600 mW of power.     

An analog front end for a two-chip 2400-bit/s voice-band modem

A complete two-chip solution comprised of an analog front end (AFE) and a general-purpose microcontroller (/spl mu/C) for a full-duplex 2400-b/s modem is discussed. The /spl mu/C performs all the necessary digital signal processing algorithms for modem signals along with providing software for modem control and the widely used AT command set. The AFE chip incorporates a ROM-based transmitter, 51 orders of filtering for channel selection, an automatic pain control circuit, and many other complex analog signal processing functions employing 65 op-amps on a 53000-mil/SUP 2/ die area with 150-mW power in a CMOS process. Design details on some of the functional blocks of the AFE are presented.