A front-end processor for modems

A front-end processor constructed of an oversampling delta-sigma ADC/DAC (analog-to-digital converter/digital-to-analog converter) and a digital signal processor is described. The chip can handle a maximum of eight different processing modes for modem applications including the echo canceling scheme. The chip incorporates a voltage reference circuit, digital PLL (phase-locked loop), and a unique second interpolation circuit to realize both conventional QAM (quadrature amplitude modulation) demodulation and echo cancel-type demodulation. The chip is fabricated in a 1.5-μm double-poly double-metal CMOS process. The chip size is 9.2 mm×7.2 mm, and the typical power consumption is 150 mW with a single +5.0-V power supply     

A system-oriented 5 V NMOS LSI circuit for data acquisition and front-end digital control

A 5 V n-channel enhancement/depletion circuit performs 8 bit data acquisition with a 5 V analog input range. It provides front-end digital control with adjustable set point and hysteresis. A simple constant-slope converter was developed, which is calibrated for a given application by tuning the built-in clock oscillator and adjusting the only reference, analog ground. For temperature compensation, the oscillator and the current source track with temperature. Digital subtraction was implemented with a three-decade synchronous BCD up/down counter, which produces positive or negative readings by a reversal of the counter. The circuit has a multiplexed three-digit TTL compatible BCD output. The chip size is 13 mm/SUP 2/ and it consumes 150 mW.     

A single-chip storage LSI for home networks

Network direct attached storage (NDAS) is a network storage architecture that allows direct attachment of existing ATA/ATAPI devices to Ethernet without a separate server. Unlike other architectures such as NAS, SAN, and USB mass storage, no server computer intervenes between the storage and the client hosts. We describe an NDAS disk controller (NDC) amenable to low-cost single-chip implementation that processes a simplified L3/L4 protocol and converts commands between ATA/ATAPI and Ethernet, while the remaining complex tasks are performed by remote hosts. Unlike NAS architectures that use TCP/IP, NDAS uses a TCP-like lean protocol that lends itself well to high-performance hardware realization. Thanks to the simple NDAS architecture and protocol, an NDC implemented on a single 4 mm /spl times/ 4 mm chip in 0.18 /spl mu/m CMOS technology achieves a maximum throughput of 55 Mbytes/s on gigabit Ethernet, which is comparable to that of a high-performance disk locally attached to a host computer.     

A single-chip NMOS dual channel filter for PCM telephony applications

The implementation of a completely monolithic channel filter containing all frequency selective functions associated with a PCM line interface is described. The circuit utilizes switched capacitor techniques. Design of the overall architecture, the individual filter sections, and the operational amplifiers in NMOS technology is described. Experimental results are presented.     

A single-chip GaAs MMIC image-rejection front-end for digitalEuropean cordless telecommunications

An active image-rejection filter is presented in this paper, which applies actively coupled passive resonators. The filter has very low noise and high insertion gain, which may eliminate the use of a low-noise amplifier (LNA) in front-end applications. The GaAs monolithic-microwave integrated-circuit (MMIC) chip area is 3.3 mm² . The filter has 12-dB insertion gain, 45-dB image rejection, 6.2-dB noise figure, and dissipates 4.3 mA from a 3-V supply. An MMIC mixer is also presented. The mixer applies two single-gate MESFETs on a 2.2-mm² GaAs substrate. The mixer has 2.5-dB conversion gain and better than 8-dB single-sideband (SSB) noise figure with a current dissipation of 3.5 mA applying a single 5-V supply. The mixer exhibits very good local oscillator (LO)/RF and LO/IF isolation of better than 30 and 17 dB, respectively, Finally, the entire front-end, including the LNA, image rejection filter, and mixer functions is realized on a 5.7-mm ² GaAs substrate. The front-end has a conversion gain of 15 dB and an image rejection of more than 53 dB with 0-dBm LO power. The SSB noise figure is better than 6.4 dB, The total power dissipation of the front-end is 33 mW. The MMIC's are applicable as a single-block LNA and image-rejection filter, mixer, and single-block front-end in digital European cordless telecommunications. With minor modifications, the MMIC's can be applied in other wireless communication systems working around 2 GHz, e.g., GSM-1800 and GSM-1900     

A highly integrated analog front-end for 3G

This paper describes a reconfigurable analog front-end (AFE) and audio codec IC supporting the wideband code division multiple access (WCDMA) standard. The chip is fabricated on Intel's 0.18-/spl mu/m (SOC) flash+logic+analog (FLA) process technology using a 0.35-/spl mu/m feature size analog transistor. The transmit path contains a 10-bit segmented rail-to-rail digital-to-analog converter, automatically tunable active RC filter, and programmable gain amplifier (PGA) with self-tuning gain and offset correction circuit. The receive path incorporates a PGA, active RC filter, and an 8-bit analog-to-digital converter with built-in offset correction. The AFE operates at 2.7 V with a current consumption of 55 mA and total active area of 15 mm/sup 2/.     

A CMOS HDSL2 analog front-end

A 5-V 0.5-μm CMOS analog front-end (AFE) IC for HDSL2 incorporates transmit digital-to-analog converter (DAC), transmit filters, output buffer, receive AGC, and receive ADC. The AFE consumes 525 mW and provides better than 82-dB signal-to-noise-and-distortion ratio (SNDR) in both transmit and receive paths. It supports variable data rates from 64 kb/s up to 2.32 Mb/s, and enables an HDSL2 system to achieve better than 14 kft of noise-free reach (on 26-gauge wire) at 1.544 Mb/s     

An adjustment-free single-chip video signal processing LSI for VHSVCR's

The authors have developed an adjustment-free single-chip video signal processing large scale integration (LSI) for VHS VCR's. This LSI's adjustment-free system was realized by using automatic feedback loop circuits. The complementary high-speed switch circuits play an important role in this system. It was possible to realize the complementary high-speed switch circuits, because this LSI has been fabricated with 2 μm bipolar process. This paper describes how the LSI has succeeded in being adjustment-free on frequency modulation (FM) carrier frequency/deviation and output video signal amplitude     

一种用于电流型电化学传感器的CMOS模拟前端芯片

本文提出了一种用于电流型电化学传感器的CMOS模拟前端芯片,芯片具有高度可编程性,其内部集成了可通过I2C接口总线与外部控制芯片通信的可配置数字模块电路。结合incremental型sigma-delta模数转换器与数字域相关双采样技术,提出并实现了一种新的两次采样的系统架构。该芯片基于华虹宏力0.18μm标准CMOS工艺流片,消耗芯片面积为1.3 mm × 1.9 mm,测试结果表明：该芯片16位数字输出具有高精度,高线性度特性,可检测溶液中磷酸根离子浓度的精度为0.01 mg/L。     

A sampled analog MOS LSI adaptive filter

Describes a novel realization of an adaptive filter using sampled analog MOS LSI techniques in which the basic functional block is an electrically programmable transversal filter whose tap weights are modified according to the least mean square algorithm. A rotating tap weight structure is used to realize a 32-tap programmable transversal filter with features for the adaptive operation included on an NMOS silicon gate chip. A wide range of magnitude and phase characteristics have been used to test this system and the results on the residual error and the convergence time under different conditions are reported. Some practical limitations are also presented.     

A CMOS modem analog processor for V.22 bis modems

A mixed analog/digital chip that forms the core of a medium-speed modem for use on the public switched telephone network is described. It meets CCITT and AT&T requirements for data transmission at 2400 and 1200 b/s, and the AT&T requirement for 300-b/s operation. The chip is implemented in a 1.75-μm analog CMOS process and occupies 32.4 mm ². The device is powered by a single +5-V supply and consumes less than 115 mW. The architecture and circuit implementation are described, and experimental results are given     

A Gm-C continuous-time anti-alias filter for UWB analog front-end

A proposed constant drain-source transconductor topology is designed to keep linearity at high frequency. By using the proposed operational transconductance amplifier as a building block, a fourth-order low-pass filter is realized. The filter was fabricated in 0.18 μm CMOS technology and feathers a 250 MHz cutoff frequency. The measured IM3 performance is ?36 dB at 0.6 V_pp input swing and the power consumption is 22 mW.     

A single-chip optical sensor with analog memory for motiondetection

A 64×64-pixel image sensor with full-frame analog memory and on-chip motion processor is presented. The processor consists of a charge amplifier and an analog subtractor. It uses the switched-capacitor technique and calculates the difference between the values of the signal on each pixel in successive frames. The rate can achieve up to 60 frames/s with limited area and power overhead. The analog memory required for the storage of the previous frame is implemented using implanted capacitors placed within the sensor array. Fabricated in a 1.2-μm standard CMOS process with an added metal 3 light-shielding layer, the circuit is fully functional and requires a total core area of 13 mm²     

A low power low noise analog front-end for ECG recording

Analog Integrated Circuits and Signal Processing - This work presents a power-efficient and noise-efficient amplifier for ECG recordings. To improve power efficiency, all the transistors in the...     

A 0.5-V low power analog front-end for heart-rate detector

This paper presents a low power analog front-end for heart-rate detector at a supply voltage of 0.5 V in 0.18 μm CMOS technology. A fully differential preamplifier is designed with a low power consumption of 300 nW. A 150 nW fourth order Switched-opamp switched capacitor bandpass filter is designed with passband 8–32 Hz. To digitize the analog signal, a low power second-order ΣΔ ADC is designed. The dynamic range and SNR of the converter are 46 dB and 54 dB respectively and it consumes a power of 125 nW. The overall front-end system including preamplifier, SO-SC bandpass filter, ΣΔ modulator and the biasing circuits are integrated and the total system consumes a power of 0.975 μW from 0.5 V supply.     

A CMOS analog front-end circuit for an FDM-based ADSL system

A CMOS analog front-end circuit for an FDM-based ADSL system is presented. The circuit contains all analog functions including AGC amplifiers, continuous-time band pass filters, ΣΔ AD/DA converters, and digital decimation and interpolation filters. On-chip automatic tuning of the bandpass filters provides more than 300% center frequency range with 1% frequency accuracy. The higher-order ΣΔ AD/DA converters achieve 12-b data conversion at 1.54 Msamples/s with an oversampling ratio of only 32. The 0.7 μm CMOS circuit measures 65 mm² and consumes 1.9 W from a single 5 V power supply     

A BiCMOS analog front-end circuit for an FDM-based ADSL system

This BiCMOS analog front-end (AFE) integrated circuit contains the analog transmit function and a low-noise receiver for FDM-based ADSL systems. The IC includes a current steered 14-bit 5-Msps D/A converter, laser trimmed third-order reconstruction and anti-alias filters, a programmable attenuator with 200-ohm output drive capability, 60-dB of RX programmable gain, and a serial interface. Trimmable thin-film resistors allow ±4% filter cutoff frequency and absolute gain accuracy. The multitone power ratio performance of the part is approximately 65 dB with a spurious free dynamic range >70 dBc. The CMRR of the RX channel is >90 dB@1.1 MHz. PSRR for transmit and receive are greater than 60 dB. The isolation features of the 1.2-μm BiCMOS technology allow transmit and receive to operate in full-duplex mode with greater than 80 dB of cross-talk isolation. The chip size is 25.8 mm² which includes bond pads and electrostatic discharge protection devices     

An analog front end for v.22bis modems

An analog front end for the 2400-b/s v.22bis modem has been implemented in a 3-μm CMOS process. A high level of integration in the front end results in a low-cost, high-performance modem system. A mix of analog switched-capacitor and digital circuits is used throughout the chip. Some of the major functional blocks are a modulator, tone generator, band-split filters, programmable receive gain stage, 8-bit ADC (analog-to-digital converters), bandgap voltage reference, and special signal detectors. Features are included to support a number of lower-speed, split-band modem standards. The chip occupies 59000 mils ² and dissipates 200 mW. System and circuit aspects of the design are discussed; measured performance of the IC and of the complete modem system are given     

Ka-band analog front-end for software-defined direct conversion receiver

A six-port Ka-band front-end architecture based on direct conversion for a software-defined radio application is proposed in this paper. The direct conversion is accomplished using six-port technology. In order to demodulate various phase-shift-keying/quadrature-amplitude-modulation (PSK/QAM) modulated signals at a high bit rate, a new analog baseband circuit was specially designed according to the I/Q equations presented in the theoretical part. An experimental prototype has been fabricated and measured. Simulation and measurement results for binary PSK, quaternary PSK (QPSK), 8 PSK, 16 PSK, and 16 QAM modulated signals at a bit rate up to 40 Mb/s are presented to validate the proposed approach. A software-defined radio can be designed using the new front-end and only two analog-to-digital converters (ADCs) because the I/Q output signals are generated by analog means. Previous six-port receivers make use of four ADCs to read the six-port dc levels and require digital computations to generate the I/Q output signals. With the proposed approach, the load of the signal processor will therefore be reduced and the modulation speed can be significantly increased using the same digital signal processor.