Voltage-balance limits in four-level diode-clamped converters with passive front ends

Multilevel diode-clamped converters with more than three levels cannot maintain voltage balance in the dc-link capacitors for some operating conditions due to the existence of dc currents in the middle points. Since capacitors are either completely charged or discharged for those conditions, this circumstance severely limits practical application of these converters. The limit explored in this paper is that the four-level converter cannot achieve voltage balance. Proper redundant vectors are selected in the space-vector diagram so that a quadratic parameter related to the currents in the middle points is minimized.     

Dynamic average-value modeling of a four-level drive system

Multilevel power converters have gained much attention in recent years due to their high power quality, low switching losses, and high-voltage capability. These advantages make the multilevel converter a candidate for the next generation of naval ship prolusion systems. Evaluation of these systems is typically assisted with a dynamic average-value models in order to rapidly predict system performance under several operating scenarios. In this paper, an average-value model is developed for the four-level diode-clamped converter which takes into account the active capacitor voltage balancing control. This model performance prediction is compared to a detailed model and laboratory measurements on an 18 kW rectifier/inverter test system.     

A Ku-band integrated receiver front end

A Ku-band integrated receiver front end has been fabricated on 20-mil aluminum oxide substrates. The receiver consists of a balanced mixer and a Gunn oscillator within an area of 0.300/spl times/0.325 inch. The performance of both packaged and unpackaged microstripline receivers is described. Using external RF tuning, a noise figure of 9 dB at 18 GHz was obtained. A higher Q Gunn oscillator design is needed for more reliable single-frequency operation.     

一种IGBT全桥逆变驱动电路的设计

简单阐述了2SC0435T模块的特点和IGBT的H桥互锁电路的特点。以2SC0435T为核心,给出了直接模式下的外围电路,以驱动IGBT全桥逆变电路。设计了栅极电阻的接法及其阻值的大小以及IGBT的栅极过压保护电路,给出了驱动信号波形,同时验证了此驱动器具有良好的保护功能和驱动功能。     

Transimpedance optical preamplifier having a common-collector front end

A simple PIN photodiode-bipolar transistor (PIN-BJT), direct-coupled, transimpedance, optical preamplifier suitable for fabrication in monolithic IC form is described. The preamplifier basically consists of a common-collector, common-emitter configuration with shunt feedback. Measurements indicate that the receiver is capable of a sensitivity of ?35.8 dBm at 140 Mbit/s for an error rate of 10?9.     

A modified current source inverter (MCSI) for a multiple inductionmotor drive system

A modified current-source inverter (MCSI) that can drive multiple motors is presented. The MCSI combines the features of the current-source inverter and the voltage-source inverter. It also overcomes major shortcomings of the current-source inverter. The commutation process of the inverter is described. Design considerations are briefly introduced. Some experimental results are given for five 1-hp induction motors running in parallel from a single MCSI     

CMOS analog front end of a transceiver with digital echocancellation for ISDN

A CMOS analog front-end which contains a novel pulse-shaping circuit, an extremely linear-line-driver state, an oversampling second-order noise-shaping coder, and a wake-up signal detector is discussed. An analog front-end for 4B 3T coded signals is realized in a 2.5-μm CMOS technology and operates up to 4.5 km with 0.4-mm-diameter lines, needing only one 5-V power supply. It is possible to transmit 2B 1Q coded signals also, using a modified pulse-shaping circuit     

A monolithic GaAs-on-Si receiver front end for optical interconnectsystems

The authors describe a monolithic technology for integrating GaAs with Si bipolar devices and demonstrate that such integration can provide improved system performance without degrading individual devices. The technology has been used to implement a 1-GHz GaAs/Si optical receiver with an equivalent input noise current density of less than 3 pA/√Hz for midband operation, and less than 4.5 pA/√Hz at 1 GHz. In this receiver an interdigitated GaAs metal-semiconductor-metal (MSM) photodetector is combined with a transimpedance preamplifier fabricated in silicon bipolar technology. The measured dark current of the GaAs/Si photodetector is 7 nA. The measured pulse response of an experimental integrated receiver is less than 550 ps FWHM. The integrated front end provides a wideband, low-noise optical receiver for use in local optical interconnections and demonstrates the successful application of integrated GaAs-on-Si technology to optoelectronics     

无线电高度表微波集成前端

研制的4.3GHz无线电高度表微波集成前端已得到实际应用,它代替了整机原用的振荡-放大一倍频方案,提高了效率、减小了体积.微波集成前端采用了高线性度FET压控振荡器作发射源,采用高隔离度的单桥路不等负载三分贝混合环混频器.在-40°～70℃的环境温度范围内发射功率大于150mW,压控带宽123MHz,线性度小于3%,接收机噪声系数小予8dB.     

A 5-GHz CMOS wireless LAN receiver front end

This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-μm CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phase-locked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm     

应用于低功耗模拟前端的可变增益放大器

为实现模拟前端电路的低功耗增益控制,提出了一种基于控制信号频宽比的可变增益放大器(variable gain amplifier,VGA),该电路以超再生为基础,能够对增益实施精细控制。与传统的大多数可变增益放大器不同的是,提出的VGA电路在数字控制和放大器之间的接口并没有使用任何的直流/交流转换器。最终实现的VGA集成电路使用了0.18 μm CMOS技术进行设计,旨在实现低功率消耗。仿真和测试结果均表明,本文提出的放大器在900 mV的线性范围内最大增益为45dB, 总谐波失真为0.5% ,功耗为6.4 ,相比传统的可变增益放大器,表现出更大的增益范围和较低的功耗。     

A dual two-level inverter scheme with common mode voltage elimination for an induction motor drive

Pulse-width modulated (PWM) inverters are known to generate common mode voltages which cause motor bearing currents in the induction motor drives. They also result in leakage currents which act as sources of conducted electromagnetic interference in the drive system. The common mode voltage generated by a conventional three-level inverter can be eliminated by switching only the voltage space vectors which do not produce the common mode voltage. This paper presents a PWM switching strategy to eliminate common mode voltage using the open-end winding configuration for the induction motor. The switching strategy presented in this paper, does not generate any alternating common mode voltages in the drive system and hence the electrostatic coupling of the common mode voltage, which results in the bearing currents and the leakage currents, is avoided. The proposed scheme is devoid of neutral point voltage fluctuations and does not require neutral point clamping diodes, when compared to the common mode elimination scheme based on the conventional three-level inverter topology. Also, the present scheme uses a single dc-link with half the voltage compared to the conventional three-level inverter based scheme.     

Active inductor based tunable multiband RF front end design for UWB applications

This study describes a new and simple frequency compensation for three stages amplifiers based on revered nested Miller compensation (RNMC) structure. Using only one and small compensation capacitor reduced circuit complexity and die area while shows better performance compared to RNMC. Also the proposed method is unconditional stable due to cancellation of second dominant pole by a zero. Ample simulations are performed using HSPICE and TSMC 0.18 µm CMOS technology to verify robustness of presented circuit. Simulation results show 114 dB, 6.66 MHz and 360 µW as DC gain, GBW and power consumption respectively.     

A 53mW IQ pipelined ADC for WLAN front end

This paper presents an analog to digital converter (ADC) architecture suitable for wideband wireless receiver system. The in-phase (I) and quadrature (Q) ADCs work independently, but share on-chip reference buffer and non-overlapped clock generation block for balance between two channels. The single ADC core consists of one front sample and hold amplifier, four cascade of 2.5 bit pipeline stages with pseudo-class AB opamp shared between adjacent stages and one 2 bit backend flash stage. The prototype was fabricated in standard 130 nm CMOS process and occupied silicon area of 0.62 mm². Performance of 66 dB spurious-free-dynamic-range is measured at 80 MS/s with 1 Vpp input signal. The power dissipation of the whole chip is only 53 mW from a 1.1 V supply.     

一种新的RFID射频前端振荡器的设计方法

为解决RFID低功耗、小体积的问题,提出了一种新的RFID射频前端振荡器的设计方法.分析了晶体管稳定性的变化规律,提出了采用晶体管和无源网络产生振荡的方法,在增加正反馈使反射系数最佳的情况下给出了振荡器的电路结构.对射频振荡器进行仿真,结果表明,调谐网络和终端网络对振荡器的性能有影响,反射系数增大可缩短起振时间,调谐网络电阻增大将加大噪声,可以综合利用史密斯圆图和复平面上的稳定性边界有效分配性能指标.研究结果为RFID在低复杂度下改善振荡器的性能提出了一种新的途径.     

A 12-bit integrated analog front end for broadband wirelinenetworks

An integrated transceiver for broadband wireline networks is presented. The transceiver includes a receive data path, a transmit data path, and auxiliary functions including serial port interface, clock and reference generation blocks, and voltage regulator control circuitry. The receive data path provides constant input impedance and is composed of two variable gain amplifier (VGA) blocks, a tuned analog 4-pole filter, a 12-b analog-to-digital converter (ADC) sampling at 32 MHz, and a digital high-pass filter. Filter tuning using switched-capacitor arrays occurs in the background, with no effect on signal reception. The transmit data path contains digital interpolation filters and a 12-b digital-to-analog converter (DAC) sampling at 128 MHz. The chip was implemented in double-poly triple-metal 0.35-μm CMOS technology. Measured performance for both receive and transmit data paths meets target specifications with no noticeable crosstalk     

一种低功耗的高速光接收器跨阻前置电路设计

为了降低芯片面积和功耗,提出了一种10 Gb/s光接收器跨阻前置放大电路。该电路采用了两个带有可调共源共栅（RGC）输入的交叉有源反馈结构,其中的跨阻放大器未使用电感,从而减少了芯片的总体尺寸。该跨阻前置电路采用0.13μm CMOS工艺设计而成,数据速率高达10 Gb/s。测试结果表明,相比其他类似电路,提出的电路芯片面积和功耗更小,芯片面积仅为0.072mm2,当电源电压为1.3 V时,功率损耗为9.1 mW,实测平均等效输入噪声电流谱密度为20pA/（0.1-10）Hz,且-3dB带宽为6.9 GHz。     

An integrated AC drive system using a controlled-current PWMrectifier/inverter link

Two identical three-phase, bipolar transistor, controlled-current, pulsewidth modulation (PWM) power modulators are integrated so that one functions as a rectifier and the other as an inverter in an AC drive system. The rectifier input currents maintain near-60-Hz sinusoidal waveforms with unity power factor. A leading power factor is also possible. The modulators do not depend on the availability of bidirectional switch elements. Performance as a polyphase induction motor drive under motoring and regenerative braking is reported. The study includes digital simulation of operation as a synchronous motor drive     

Three-level inverter configuration with common mode voltage elimination for induction motor drive

A scheme for a three-level voltage space phasor generation with common-mode voltage elimination is proposed. An open-end-winding induction motor, fed from both ends by two three-level inverters, which are realized by a cascading two two-level inverter, is used in this configuration. The voltage space vectors of individual three- level inverters, which generate the same common mode voltage in the inverter pole voltage, are variously grouped When these voltage space vectors are used to switch individual three-level inverters, it results in zero commonmode voltage across the motor windings. In the proposed scheme, voltage space phasors from individual inverters with zero common mode voltage in the inverter pole voltage are used for PWM control. For the proposed drive configuration, the DC link voltage requirement is only half when compared to the DC link voltage of a conventional neutral-point-clamped （NPC） three-level inverter. The proposed inverter configuration offers reduced circuit and control complexity when compared to similar schemes with NPC or H-bridge inverter configurations.