共查询到20条相似文献,搜索用时 31 毫秒
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寄生电容是叠层片式电感器的重要参数,对电感器的Q值和谐振频率影响很大.如何准确估计寄生电容的大小成为电感器设计的一个难题.采用Ansoft Q3D软件建立了叠层片式陶瓷电感器的3D静电场有限元模型,计算了各电极间的杂散电容,然后建立电感器的等效电容网络,列出节点电压方程并求解得到寄生电容.计算结果和测量结果基本一致.瓷... 相似文献
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利用了集成芯片AD7150完成了对微位移电容传感器的电容采样。对AD7150芯片设计了相应的外接电路,为了增强电路的抗干扰能力,加入相应滤波电路;通过单片机模拟I2C通信方式来进行AD7150的读写控制。测量结果给出了10 pF以下不同标称电容值的电容,误差在2.5%以内。初步实验结果表明,当接入双叉电容传感器探头时,电容值随测量距离的增大而增加;在不同位移量下,传感器的灵敏度不同,距离越近,灵敏度越高,最大灵敏度为686 fF/mm,给出了不同情况下的灵敏度分布,并总结了影响电容传感器工作的电路要点。 相似文献
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《Semiconductor Manufacturing, IEEE Transactions on》2009,22(1):96-102
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运用电容触摸检测芯片CP2512与单片机S3F9488进行电路设计.触摸检测芯片CP2512通过检测电容的变化量来感知外界数据的变化,通过I2C协议把CP2512采集的数据送到S3F9488,S3F9488根据采集到的数据进行相应的功率控制.本文给出了CP2512与S3F9488的硬件设计图.该方案的设计可以使家电产品更加耐用、美观;能有效地提高产品的抗干扰能力,提升产品的品质.该电路的设计为家电产品提够了一种低成本解决方案,最终在电磁炉中得到了实现. 相似文献
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介绍了一种应用于模拟卫星电视调谐器的单端晶体OSC实现方法,本结构所有负载电容都集成在片内,片外只需连接晶体的单个管脚,片内所有电容都由MOS管栅电容实现,从而大大减小了芯片的面积,在0.18μm1P6MCMOS工艺下,整体版图面积只有0.023mm2.电路可实现外接晶体模式或外接激励模式自由切换,外接晶体时可在2-10M晶体下正常工作,振荡稳定产生轨到轨正弦波形,起振时间在1ms内,外接激励模式下可满足0.1~3.3V的正弦波输入. 相似文献
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针对北方地区冬季暖气管道漏水可能导致的大型设备机房或重要仪器损坏的问题,提出了一种用于管道漏水检测的单一平面电容式传感器的设计方案。该装置利用平面电容原理,检测水滴落在平面电容上时引起的电容变化,采用微电容测量电路将电容转换成频率,然后通过单片机处理后计算出电容值,通过和预先设定的阈值电容的比较来判断平板上是否漏水。经实际试验,该方案实施的平面电容式漏水检测传感器应用于管道漏水检测具有结构简单、成本便宜、性能可靠的特点。 相似文献
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《Electron Devices, IEEE Transactions on》1976,23(2):93-101
A new practical form of charge-coupled device (CCD) memory structure is described which achieves high storage density while providing low clock-line capacitance. In the new structure, the time-division multiplexing of multiphase concepts is replaced by the spatial multiplexing of a serial-parallel-serial (SPS) array. By using a ring counter to generate the multiphase clocking, a compact method of clock generation is described which allows the integration of multiphase drivers into the memory array. The improved density results from using a multiphase technique while the low clock-line capacitance stems from integrating the necessary drivers into the memory structure. The average bit density of the new structure including all necessary drivers exceeds that of previously discussed CCD memory structures when similar layout rules and gate electrode configurations are applied. A 4096-bit memory chip was built to fully demonstrate the new multiphase serial-parallel-serial storage (MSPS). The memory chip additionally uses serial decoding to increase the ratio of bit storage area to decoding circuitry area. The memory chip performed all memory functions of READ, WRITE, and REFRESH. The memory is organized into 16 separate 256-bit CCD shift registers. It is also found that interlacing is effective in increasing the average bit density in MSPS structures. The combination of high density and low drive capacitance makes the MSPS structure appear attractive for memory applications. 相似文献
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Eslami Y. Sheikholeslami A. Masui S. Endo T. Kawashima S. 《Solid-State Circuits, IEEE Journal of》2004,39(11):2024-2031
This paper presents two circuit implementations for the differential capacitance read scheme (DCRS) in ferroelectric random-access memories (FeRAM). Compared to the conventional read scheme, DCRS achieves a faster read access by activating the sense amplifiers immediately after a wordline is activated. By relying on the capacitance difference instead of the charge difference, DCRS avoids raising the highly capacitive platelines until after the read is complete. We have implemented this scheme in a 0.35-/spl mu/m CMOS+Ferro test chip that includes an array of 256 /spl times/ 32 2T-2C cells. The test chip measures an access time of 45 ns at a power supply of 3 V. 相似文献
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A novel GaInAs substrate illuminated photodetector structure is reported for the 1.0?1.7 ?m wavelength range with capacitance as low as 0.02 pF, packaging stray capacitance below 0.02 pF, 97% quantum efficiency and subnanoampere leakage current. The device is rugged, epoxy-free, does not use an integral fibre pig-tail and wire bonding to the detector chip is not required. 相似文献
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提出一种电容片内集成、高效率升压模式的DC-DC电源管理芯片,较普通结构相比,文中提出的电路结构具有6组2×,3组3×,2组4×升压模型共11种工作模式,并具有低纹波等优点。通过MIM电容与积累型NMOS电容串联的方式,提高单位面积容值,使得总电容面积大幅减小。采用SMIC 0.18μm CMOS工艺,利用Cadence工具对电路进行仿真验证,所提出自适应开关电容升压电路,在输出电压为3 V时,其效率最高可达到83.6%。在开关频率为20 MHz时,输入电压范围为1~1.8 V,所需总片内集成电容总面积为900 μm×900 μm,输出电压纹波<40 mV 相似文献
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Sergio M. Manaresi N. Campi F. Canegallo R. Tartagni M. Guerrieri R. 《Solid-State Circuits, IEEE Journal of》2003,38(6):966-975
This paper presents a mixed-signal system-on-chip (SOC) for sensing capacitance variations, enabling the creation of pressure-sensitive fabric. The chip is designed to sit in the corner of a smart fabric such as elastic foam overlaid with a matrix of conductive threads. When pressure is applied to the matrix, an image is created from measuring the differences in capacitance among the rows and columns of fibers patterned on the two opposite sides of the elastic substrate. The SOC approach provides the flexibility to accommodate for different fabric sizes and to perform image enhancement and on-chip data processing. The chip has been designed in a 0.35-/spl mu/m five-metal one-poly CMOS process working up to 40 MHz at 3.3 V of power supply, in a fully reconfigurable arrangement of 128 I/O lines. The core area is 32 mm/sup 2/. 相似文献
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基于0.6μm CMOS混合信号工艺设计了一款高稳定度、宽电源电压范围的晶体振荡器芯片。该芯片片内集成具有优异频率响应的振荡器电容和反馈电阻,只需外接石英晶体即可提供高稳定时钟源。测试结果表明:芯片最高工作频率可达40MHz;在振荡频率12MHz、负载电容15pF、电源电压从2.7V到5.5V变化时其频率随电源电压变化率小于1×10-6;电源电压为5V时芯片消耗总电流小于4mA。 相似文献
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In this paper, a three axis accelerometer is successfully developed by a mixing-mode chip design using CMOS surface-micromachining technology. The chip consists of mass-spring, the analog core and the digital circuit. The vibration sensor is implemented with micro-spring to change the capacitance between two metals. The analog core detects the capacitance differential to the frequency shifting using an oscillator. The digital control is to compute the amount of acceleration to the form of digital bit. The chip can detect the acceleration to 140 g for x axis and y axis with 10-bit resolution, and from 110 g for z axis with 9 bits. The detected speed is about 4 k bits per second, for three-axis output in parallel. The chip size is about 1,400 × 1,400 um2, when TSMC 0.18 um 1P6 M process is employed. This 3D accelerometer can directly connect to the digital interface with three serial-port output for the information of X, Y and Z axis. 相似文献
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Ruggedness, wide capacitance range, high volumetric efficiency, and relatively attractive cost have been the main reasons for the popularity of ceramic chip capacitors. Continuing improvements in most of these categories promise to keep the ceramic chip in its present position of prominence. This article considers multilayer, single-layer, and screened-on configurations. In addition, relationships between size, capacitance, and cost are covered for three common ceramic formulations (NPO, W5R, and Z5U). 相似文献