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为了提高功率器件结终端击穿电压,节约芯片面积,设计了一款700 V VDMOSFET结终端结构。在不增加额外工艺步骤和掩膜的前提下,该结构采用场限环-场板联合结终端技术,通过调整结终端场限环和场板的结构参数,在151μm的有效终端长度上达到了772 V的击穿电压,表面电场分布相对均匀且最大表面场强为2.27×105V/cm,小于工业界判断器件击穿场强标准(2.5×105 V/cm)。在保证相同的击穿电压下,比其他文献中同类结终端结构节约面积26%,实现了耐压和可靠性的要求,提高了结终端面积的利用效率。 相似文献
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为了改善硅功率器件击穿电压性能以及改善IGBT电流的流动方向,提出了一种沟槽-场限环复合终端结构。分别在主结处引入浮空多晶硅沟槽,在场限环的左侧引入带介质的沟槽,沟槽右侧与场限环左侧横向扩展界面刚好交接。结果表明,这一结构改善了IGBT主结电流丝分布,将一部分电流路径改为纵向流动,改变了碰撞电离路径,在提高主结电势的同时也提高器件终端结构的可靠性;带介质槽的场限环结构进一步缩短了终端长度,其横纵耗尽比为3.79,较传统设计的场限环结构横纵耗尽比减少了1.48%,硅片利用率提高,进而减小芯片面积,节约制造成本。此方法在场限环终端设计中非常有效。 相似文献
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垂直双扩散金属氧化物场效应晶体管(Vertical Double-diffused Metal-Oxide-Semiconductor Field Effect Transistor,VDMOS)终端设计中,场限环结构被广泛应用,但随着器件耐压的增加,场限环终端在效率、占用面积方面的劣势也越发明显。结合横向变掺杂的原理,在成熟的场限环工艺基础上,只更改深阱杂质注入窗口大小与距离,设计了一种800 V VDMOS终端结构,击穿电压仿真值达到938.5 V,为平行平面结击穿电压的93.29%,有效终端长度仅为137.4 μm。 相似文献
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场板与场限环是用来提高功率FRED抗电压击穿能力的常用终端保护技术,本文分别介绍场板与场限环结终端结构原理和耐压敏感参数,然后采取场板和场限环的互补组合,通过Synopsis公司MEDICI4.0仿真工具优化设一款耐压1200V的FERD器件终端结构,最后通过实际流片验证此终端结构具有良好的电压重复性及一致性。 相似文献
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一种新型高压功率器件终端技术 总被引:3,自引:1,他引:2
为了改善高压功率器件的击穿电压、节省芯片面积,提出一种P-场限环结合P+补偿结构、同时与金属偏移场板技术相结合的高压终端技术.采用TCAD(ISE)时该技术进行模拟,结果表明,该技术具有比较好的面积优化和击穿电压优化特性. 相似文献
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为使3300 V及以上电压等级绝缘栅双极型晶体管(IGBT)的工作结温达到150℃以上,设计了一种具有高结终端效率、结构简单且工艺可实现的线性变窄场限环(LNFLR)终端结构。采用TCAD软件对这种终端结构的击穿电压、电场分布和击穿电流等进行了仿真,调整环宽、环间距及线性变窄的公差值等结构参数以获得最优的电场分布,重点对比了高环掺杂浓度和低环掺杂浓度两种情况下LNFLR终端的阻断特性。仿真结果表明,低环掺杂浓度的LNFLR终端具有更高的击穿电压。进一步通过折中击穿电压和终端宽度,采用LNFLR终端的3300 V IGBT器件可以实现4500 V以上的终端耐压,而终端宽度只有700μm,相对于标准的场限环场板(FLRFP)终端缩小了50%。 相似文献
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基于垂直双扩散金属氧化物(VDMOS)场效应晶体管终端场限环(FLR)与场板(FP)理论,在场限环上依次添加金属场板与多晶硅场板,并通过软件仿真对其进行参数优化,最终实现了一款700 V VDMOS终端结构的优化设计。对比场限环终端结构,金属场板与多晶硅复合场板的终端结构,能够更加有效地降低表面电场峰值,增强环间耐压能力,从而减少场限环个数并增大终端击穿电压。终端有效长度仅为145μm,击穿电压能够达到855.0 V,表面电场最大值为2.0×105V/cm,且分布比较均匀,终端稳定性和可靠性高。此外,没有增加额外掩膜和其他工艺步骤,工艺兼容性好,易于实现。 相似文献
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The most commonly used high-voltage blocking and termination structures-floating field limiting rings (FLR), lateral charge control HVIC devices, and junction termination extension (JTE) structures-are very sensitive to positive silicon and silicon dioxide interface charges. These high-voltage termination structures specifically designed for 1000-V blocking capability lose 25 to 50% of their voltage-blocking capability under 5×1011 cm-2 net interface state density. In contrast, optimized multiple-zone JTE (MZ-JTE), and offset multiple field plated and field-limiting ring (OFP-FLR) structures will lose only 5% of their respective voltage blocking capabilities under the same surface-charge condition. These improved high-voltage blocking structures do not require additional passivation and process complexities 相似文献
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Numerical simulations on the optimization of junction termination extension (JTE) have been performed. Various termination techniques have been applied and simulated in this paper, such as single-zone JTE (S-JTE), multi-zone JTE (M-JTE), and space-modulated JTE (SM-JTE). A completely novel and efficient method is demonstrated in this paper to determine total length of SM-JTE, and it is verified through simulation results. The simulation results show that the SM-JTE could provide a protection efficiency (defined in Section 2) of 95.2%, which is much higher than that of M-JTE (82.4%) and S-JTE (64.7%). Based on the fabricated MOSFETs, the interface charge density is extracted and the approximate range of charge density has been determined. The influences of different interface charge densities have been investigated for the three termination techniques respectively. According to the previous reports, the JTE is quite sensitive to the implanted dose, so the blocking capability of each termination structure with different implanted doses is also simulated. The results show that when interface charge is considered, the SM-JTE always shows an enormous advantage over the other two junction termination structures, however the interface charge densities varied. The space-modulated JTE is also applicable to the power planar devices such as MOSFETs and IGBTs, which would provide a very promising lower fabrication cost. 相似文献
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Juntao Li Chengquan Xiao Xingliang Xu Gang Dai Lin Zhang Yang Zhou An Xiang Yingkun Yang Jian Zhang 《半导体学报》2017,38(2):024003-4
This paper presents the design and fabrication of an etched implant junction termination extension(JTE) for high-voltage 4H-SiC PiN diodes. Unlike the conventional JTE structure, the proposed structure utilizes multiple etching steps to achieve the optimum JTE concentration range. The simulation results show that the etched implant JTE method can improve the blocking voltage of SiC PiN diodes and also provides broad process latitude for parameter variations, such as implantation dose and activation annealing condition. The fabricated SiC PiN diodes with the etched implant JTE exhibit a highest blocking voltage of 4.5 kV and the forward on-state voltage of 4.6 V at room temperature. These results are of interest for understanding the etched implant method in the fabrication of high-voltage power devices. 相似文献
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According to the avalanche ionization theory,a computer-based analysis is performed to analyze the structural parameters of single-and multiple-zone junction termination extension (JTE) structures for 4H-SiC bipolar junction transistors (BJTs) with mesa structure.The calculation results show that a single-zone JTE can yield high breakdown voltages if the activated JTE dose and the implantation width are controlled precisely and a multiple-zone JTE method can decrease the peak surface field while still maintaining a high blocking capability.The influences of the positive and negative surface or interface states on the blocking capability are also shown.These conclusions have a realistic meaning in optimizing the design of a mesa power device. 相似文献
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按照功率VDMOSFET正向设计的思路,选取(100)晶向的衬底硅片,采用多晶硅栅自对准工艺,结合MEDICI器件仿真和SUPREM-4工艺仿真软件,提取参数结果,并最终完成工艺产品试制,达到了500 V/8 A高压、大电流VDMOSFET的设计与研制要求。结果证明,通过计算机模拟仿真,架起了理论分析与实际产品试制之间的桥梁。相对于原来小批量投片、反复试制的方法,不仅节约了时间,降低了研制成本,而且模拟结果与实际试制结果之间能够较好地吻合。针对传统结终端结构的弊端,提出了一种新型结终端结构,大大提高了产品的击穿电压和可靠性。 相似文献
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对常用的场限环(FLR)和正、负斜角终端结构的耐压机理进行了简要分析,讨论了其结构参数的优化方法.基于GTR台面终端结构,在功率MOSFET中引入了一种类似的沟槽负斜角终端结构.利用1SE软件对其耐压机理和击穿特性进行了模拟与分析.结果表明,采用沟槽负斜角终端结构会使功率MOSFET的耐压达到其平行平面结击穿电压的92... 相似文献
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在对4H-SiC高压PIN二极管进行了理论分析的基础上,利用仿真软件ISE10.0对具有结终端保护的高压4H-SiC PIN二极管耐压特性进行了模拟仿真计算,并取得了很多有价值的计算结果。利用平面制造工艺,结合仿真提取的参数,试制了高压4H-SiC PIN二极管。实验测试结果表明,仿真计算的结果与实际样品测试的数据一致性较好,实测此器件击穿电压值已达到1 650V。 相似文献
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在半导体高压终端研究中,重要的工作之一是终端电场电位分析。国内外以往报道的JTE分析结果除采用解析方法外,数值方法主要采用差分或有限元法。作者利用边界元数值技术,采用“边界元临界电场分析法”,用自主开发的统一的边界元终端分析软件,从新的角度,以单区、双区JTE为例,详细讨论了新的边界元分析法,研究了极值电场分布等情况,得到了物理概念清晰,描述较准确而又简明直观的优化结果。边界元算法独特,优点显著。现有程序不但可用于JTE终端优化分析设计,还可直接用于场板、JTE加场板等终端结构场分析。 相似文献